442 lines
28 KiB
TableGen
442 lines
28 KiB
TableGen
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//===- AArch64SchedPredicates.td - AArch64 Sched Preds -----*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines scheduling predicate definitions that are used by the
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// AArch64 subtargets.
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//
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//===----------------------------------------------------------------------===//
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// Function mappers.
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// Check the extension type in arithmetic instructions.
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let FunctionMapper = "AArch64_AM::getArithExtendType" in {
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def CheckExtUXTB : CheckImmOperand_s<3, "AArch64_AM::UXTB">;
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def CheckExtUXTH : CheckImmOperand_s<3, "AArch64_AM::UXTH">;
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def CheckExtUXTW : CheckImmOperand_s<3, "AArch64_AM::UXTW">;
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def CheckExtUXTX : CheckImmOperand_s<3, "AArch64_AM::UXTX">;
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def CheckExtSXTB : CheckImmOperand_s<3, "AArch64_AM::SXTB">;
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def CheckExtSXTH : CheckImmOperand_s<3, "AArch64_AM::SXTH">;
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def CheckExtSXTW : CheckImmOperand_s<3, "AArch64_AM::SXTW">;
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def CheckExtSXTX : CheckImmOperand_s<3, "AArch64_AM::SXTX">;
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}
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// Check for shifting in extended arithmetic instructions.
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foreach I = {0-3} in {
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let FunctionMapper = "AArch64_AM::getArithShiftValue" in
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def CheckExtBy#I : CheckImmOperand<3, I>;
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}
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// Check the extension type in the register offset addressing mode.
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let FunctionMapper = "AArch64_AM::getMemExtendType" in {
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def CheckMemExtUXTW : CheckImmOperand_s<3, "AArch64_AM::UXTW">;
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def CheckMemExtLSL : CheckImmOperand_s<3, "AArch64_AM::UXTX">;
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def CheckMemExtSXTW : CheckImmOperand_s<3, "AArch64_AM::SXTW">;
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def CheckMemExtSXTX : CheckImmOperand_s<3, "AArch64_AM::SXTX">;
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}
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// Check for scaling in the register offset addressing mode.
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let FunctionMapper = "AArch64_AM::getMemDoShift" in
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def CheckMemScaled : CheckImmOperandSimple<4>;
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// Check the shifting type in arithmetic and logic instructions.
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let FunctionMapper = "AArch64_AM::getShiftType" in {
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def CheckShiftLSL : CheckImmOperand_s<3, "AArch64_AM::LSL">;
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def CheckShiftLSR : CheckImmOperand_s<3, "AArch64_AM::LSR">;
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def CheckShiftASR : CheckImmOperand_s<3, "AArch64_AM::ASR">;
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def CheckShiftROR : CheckImmOperand_s<3, "AArch64_AM::ROR">;
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def CheckShiftMSL : CheckImmOperand_s<3, "AArch64_AM::MSL">;
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}
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// Check for shifting in arithmetic and logic instructions.
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foreach I = {0-3, 8} in {
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let FunctionMapper = "AArch64_AM::getShiftValue" in
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def CheckShiftBy#I : CheckImmOperand<3, I>;
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}
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// Generic predicates.
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// Identify whether an instruction is the 16-bit NEON form based on its result.
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def CheckHForm : CheckAll<[CheckIsRegOperand<0>,
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CheckAny<[CheckRegOperand<0, H0>,
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CheckRegOperand<0, H1>,
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CheckRegOperand<0, H2>,
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CheckRegOperand<0, H3>,
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CheckRegOperand<0, H4>,
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CheckRegOperand<0, H5>,
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CheckRegOperand<0, H6>,
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CheckRegOperand<0, H7>,
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CheckRegOperand<0, H8>,
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CheckRegOperand<0, H9>,
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CheckRegOperand<0, H10>,
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CheckRegOperand<0, H11>,
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CheckRegOperand<0, H12>,
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CheckRegOperand<0, H13>,
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CheckRegOperand<0, H14>,
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CheckRegOperand<0, H15>,
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CheckRegOperand<0, H16>,
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CheckRegOperand<0, H17>,
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CheckRegOperand<0, H18>,
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CheckRegOperand<0, H19>,
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CheckRegOperand<0, H20>,
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CheckRegOperand<0, H21>,
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CheckRegOperand<0, H22>,
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CheckRegOperand<0, H23>,
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CheckRegOperand<0, H24>,
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CheckRegOperand<0, H25>,
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CheckRegOperand<0, H26>,
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CheckRegOperand<0, H27>,
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CheckRegOperand<0, H28>,
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CheckRegOperand<0, H29>,
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CheckRegOperand<0, H30>,
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CheckRegOperand<0, H31>]>]>;
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// Identify whether an instruction is the 32-bit NEON form based on its result.
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def CheckSForm : CheckAll<[CheckIsRegOperand<0>,
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CheckAny<[CheckRegOperand<0, S0>,
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CheckRegOperand<0, S1>,
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CheckRegOperand<0, S2>,
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CheckRegOperand<0, S3>,
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CheckRegOperand<0, S4>,
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CheckRegOperand<0, S5>,
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CheckRegOperand<0, S6>,
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CheckRegOperand<0, S7>,
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CheckRegOperand<0, S8>,
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CheckRegOperand<0, S9>,
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CheckRegOperand<0, S10>,
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CheckRegOperand<0, S11>,
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CheckRegOperand<0, S12>,
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CheckRegOperand<0, S13>,
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CheckRegOperand<0, S14>,
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CheckRegOperand<0, S15>,
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CheckRegOperand<0, S16>,
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CheckRegOperand<0, S17>,
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CheckRegOperand<0, S18>,
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CheckRegOperand<0, S19>,
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CheckRegOperand<0, S20>,
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CheckRegOperand<0, S21>,
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CheckRegOperand<0, S22>,
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CheckRegOperand<0, S23>,
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CheckRegOperand<0, S24>,
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CheckRegOperand<0, S25>,
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CheckRegOperand<0, S26>,
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CheckRegOperand<0, S27>,
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CheckRegOperand<0, S28>,
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CheckRegOperand<0, S29>,
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CheckRegOperand<0, S30>,
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CheckRegOperand<0, S31>]>]>;
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// Identify whether an instruction is the 64-bit NEON form based on its result.
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def CheckDForm : CheckAll<[CheckIsRegOperand<0>,
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CheckAny<[CheckRegOperand<0, D0>,
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CheckRegOperand<0, D1>,
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CheckRegOperand<0, D2>,
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CheckRegOperand<0, D3>,
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CheckRegOperand<0, D4>,
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CheckRegOperand<0, D5>,
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CheckRegOperand<0, D6>,
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CheckRegOperand<0, D7>,
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CheckRegOperand<0, D8>,
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CheckRegOperand<0, D9>,
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CheckRegOperand<0, D10>,
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CheckRegOperand<0, D11>,
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CheckRegOperand<0, D12>,
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CheckRegOperand<0, D13>,
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CheckRegOperand<0, D14>,
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CheckRegOperand<0, D15>,
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CheckRegOperand<0, D16>,
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CheckRegOperand<0, D17>,
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CheckRegOperand<0, D18>,
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CheckRegOperand<0, D19>,
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CheckRegOperand<0, D20>,
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CheckRegOperand<0, D21>,
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CheckRegOperand<0, D22>,
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CheckRegOperand<0, D23>,
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CheckRegOperand<0, D24>,
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CheckRegOperand<0, D25>,
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CheckRegOperand<0, D26>,
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CheckRegOperand<0, D27>,
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CheckRegOperand<0, D28>,
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CheckRegOperand<0, D29>,
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CheckRegOperand<0, D30>,
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CheckRegOperand<0, D31>]>]>;
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// Identify whether an instruction is the 128-bit NEON form based on its result.
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def CheckQForm : CheckAll<[CheckIsRegOperand<0>,
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CheckAny<[CheckRegOperand<0, Q0>,
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CheckRegOperand<0, Q1>,
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CheckRegOperand<0, Q2>,
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CheckRegOperand<0, Q3>,
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CheckRegOperand<0, Q4>,
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CheckRegOperand<0, Q5>,
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CheckRegOperand<0, Q6>,
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CheckRegOperand<0, Q7>,
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CheckRegOperand<0, Q8>,
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CheckRegOperand<0, Q9>,
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CheckRegOperand<0, Q10>,
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CheckRegOperand<0, Q11>,
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CheckRegOperand<0, Q12>,
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CheckRegOperand<0, Q13>,
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CheckRegOperand<0, Q14>,
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CheckRegOperand<0, Q15>,
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CheckRegOperand<0, Q16>,
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CheckRegOperand<0, Q17>,
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CheckRegOperand<0, Q18>,
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CheckRegOperand<0, Q19>,
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CheckRegOperand<0, Q20>,
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CheckRegOperand<0, Q21>,
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CheckRegOperand<0, Q22>,
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CheckRegOperand<0, Q23>,
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CheckRegOperand<0, Q24>,
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CheckRegOperand<0, Q25>,
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CheckRegOperand<0, Q26>,
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CheckRegOperand<0, Q27>,
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CheckRegOperand<0, Q28>,
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CheckRegOperand<0, Q29>,
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CheckRegOperand<0, Q30>,
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CheckRegOperand<0, Q31>]>]>;
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// Identify arithmetic instructions with extend.
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def IsArithExtOp : CheckOpcode<[ADDWrx, ADDXrx, ADDSWrx, ADDSXrx,
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SUBWrx, SUBXrx, SUBSWrx, SUBSXrx,
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ADDXrx64, ADDSXrx64,
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SUBXrx64, SUBSXrx64]>;
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// Identify arithmetic immediate instructions.
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def IsArithImmOp : CheckOpcode<[ADDWri, ADDXri, ADDSWri, ADDSXri,
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SUBWri, SUBXri, SUBSWri, SUBSXri]>;
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// Identify arithmetic instructions with shift.
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def IsArithShiftOp : CheckOpcode<[ADDWrs, ADDXrs, ADDSWrs, ADDSXrs,
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SUBWrs, SUBXrs, SUBSWrs, SUBSXrs]>;
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// Identify arithmetic instructions without shift.
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def IsArithUnshiftOp : CheckOpcode<[ADDWrr, ADDXrr, ADDSWrr, ADDSXrr,
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SUBWrr, SUBXrr, SUBSWrr, SUBSXrr]>;
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// Identify logic immediate instructions.
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def IsLogicImmOp : CheckOpcode<[ANDWri, ANDXri,
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EORWri, EORXri,
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ORRWri, ORRXri]>;
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// Identify logic instructions with shift.
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def IsLogicShiftOp : CheckOpcode<[ANDWrs, ANDXrs, ANDSWrs, ANDSXrs,
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BICWrs, BICXrs, BICSWrs, BICSXrs,
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EONWrs, EONXrs,
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EORWrs, EORXrs,
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ORNWrs, ORNXrs,
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ORRWrs, ORRXrs]>;
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// Identify logic instructions without shift.
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def IsLogicUnshiftOp : CheckOpcode<[ANDWrr, ANDXrr, ANDSWrr, ANDSXrr,
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BICWrr, BICXrr, BICSWrr, BICSXrr,
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EONWrr, EONXrr,
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EORWrr, EORXrr,
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ORNWrr, ORNXrr,
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ORRWrr, ORRXrr]>;
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// Identify arithmetic and logic immediate instructions.
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def IsArithLogicImmOp : CheckOpcode<!listconcat(IsArithImmOp.ValidOpcodes,
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IsLogicImmOp.ValidOpcodes)>;
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// Identify arithmetic and logic instructions with shift.
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def IsArithLogicShiftOp : CheckOpcode<!listconcat(IsArithShiftOp.ValidOpcodes,
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IsLogicShiftOp.ValidOpcodes)>;
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// Identify arithmetic and logic instructions without shift.
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def IsArithLogicUnshiftOp : CheckOpcode<!listconcat(IsArithUnshiftOp.ValidOpcodes,
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IsLogicUnshiftOp.ValidOpcodes)>;
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// Identify whether an instruction is an ASIMD
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// load using the post index addressing mode.
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def IsLoadASIMDPostOp : CheckOpcode<[LD1Onev8b_POST, LD1Onev4h_POST, LD1Onev2s_POST, LD1Onev1d_POST,
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LD1Onev16b_POST, LD1Onev8h_POST, LD1Onev4s_POST, LD1Onev2d_POST,
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LD1Twov8b_POST, LD1Twov4h_POST, LD1Twov2s_POST, LD1Twov1d_POST,
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LD1Twov16b_POST, LD1Twov8h_POST, LD1Twov4s_POST, LD1Twov2d_POST,
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LD1Threev8b_POST, LD1Threev4h_POST, LD1Threev2s_POST, LD1Threev1d_POST,
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LD1Threev16b_POST, LD1Threev8h_POST, LD1Threev4s_POST, LD1Threev2d_POST,
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LD1Fourv8b_POST, LD1Fourv4h_POST, LD1Fourv2s_POST, LD1Fourv1d_POST,
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LD1Fourv16b_POST, LD1Fourv8h_POST, LD1Fourv4s_POST, LD1Fourv2d_POST,
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LD1i8_POST, LD1i16_POST, LD1i32_POST, LD1i64_POST,
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LD1Rv8b_POST, LD1Rv4h_POST, LD1Rv2s_POST, LD1Rv1d_POST,
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LD1Rv16b_POST, LD1Rv8h_POST, LD1Rv4s_POST, LD1Rv2d_POST,
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LD2Twov8b_POST, LD2Twov4h_POST, LD2Twov2s_POST,
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LD2Twov16b_POST, LD2Twov8h_POST, LD2Twov4s_POST, LD2Twov2d_POST,
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LD2i8_POST, LD2i16_POST, LD2i32_POST, LD2i64_POST,
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LD2Rv8b_POST, LD2Rv4h_POST, LD2Rv2s_POST, LD2Rv1d_POST,
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LD2Rv16b_POST, LD2Rv8h_POST, LD2Rv4s_POST, LD2Rv2d_POST,
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LD3Threev8b_POST, LD3Threev4h_POST, LD3Threev2s_POST,
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LD3Threev16b_POST, LD3Threev8h_POST, LD3Threev4s_POST, LD3Threev2d_POST,
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LD3i8_POST, LD3i16_POST, LD3i32_POST, LD3i64_POST,
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LD3Rv8b_POST, LD3Rv4h_POST, LD3Rv2s_POST, LD3Rv1d_POST,
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LD3Rv16b_POST, LD3Rv8h_POST, LD3Rv4s_POST, LD3Rv2d_POST,
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LD4Fourv8b_POST, LD4Fourv4h_POST, LD4Fourv2s_POST,
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LD4Fourv16b_POST, LD4Fourv8h_POST, LD4Fourv4s_POST, LD4Fourv2d_POST,
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LD4i8_POST, LD4i16_POST, LD4i32_POST, LD4i64_POST,
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LD4Rv8b_POST, LD4Rv4h_POST, LD4Rv2s_POST, LD4Rv1d_POST,
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LD4Rv16b_POST, LD4Rv8h_POST, LD4Rv4s_POST, LD4Rv2d_POST]>;
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// Identify whether an instruction is an ASIMD
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// store using the post index addressing mode.
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def IsStoreASIMDPostOp : CheckOpcode<[ST1Onev8b_POST, ST1Onev4h_POST, ST1Onev2s_POST, ST1Onev1d_POST,
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ST1Onev16b_POST, ST1Onev8h_POST, ST1Onev4s_POST, ST1Onev2d_POST,
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ST1Twov8b_POST, ST1Twov4h_POST, ST1Twov2s_POST, ST1Twov1d_POST,
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ST1Twov16b_POST, ST1Twov8h_POST, ST1Twov4s_POST, ST1Twov2d_POST,
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ST1Threev8b_POST, ST1Threev4h_POST, ST1Threev2s_POST, ST1Threev1d_POST,
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ST1Threev16b_POST, ST1Threev8h_POST, ST1Threev4s_POST, ST1Threev2d_POST,
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ST1Fourv8b_POST, ST1Fourv4h_POST, ST1Fourv2s_POST, ST1Fourv1d_POST,
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ST1Fourv16b_POST, ST1Fourv8h_POST, ST1Fourv4s_POST, ST1Fourv2d_POST,
|
||
|
|
ST1i8_POST, ST1i16_POST, ST1i32_POST, ST1i64_POST,
|
||
|
|
ST2Twov8b_POST, ST2Twov4h_POST, ST2Twov2s_POST,
|
||
|
|
ST2Twov16b_POST, ST2Twov8h_POST, ST2Twov4s_POST, ST2Twov2d_POST,
|
||
|
|
ST2i8_POST, ST2i16_POST, ST2i32_POST, ST2i64_POST,
|
||
|
|
ST3Threev8b_POST, ST3Threev4h_POST, ST3Threev2s_POST,
|
||
|
|
ST3Threev16b_POST, ST3Threev8h_POST, ST3Threev4s_POST, ST3Threev2d_POST,
|
||
|
|
ST3i8_POST, ST3i16_POST, ST3i32_POST, ST3i64_POST,
|
||
|
|
ST4Fourv8b_POST, ST4Fourv4h_POST, ST4Fourv2s_POST,
|
||
|
|
ST4Fourv16b_POST, ST4Fourv8h_POST, ST4Fourv4s_POST, ST4Fourv2d_POST,
|
||
|
|
ST4i8_POST, ST4i16_POST, ST4i32_POST, ST4i64_POST]>;
|
||
|
|
|
||
|
|
// Identify whether an instruction is an ASIMD load
|
||
|
|
// or store using the post index addressing mode.
|
||
|
|
def IsLoadStoreASIMDPostOp : CheckOpcode<!listconcat(IsLoadASIMDPostOp.ValidOpcodes,
|
||
|
|
IsStoreASIMDPostOp.ValidOpcodes)>;
|
||
|
|
|
||
|
|
// Identify whether an instruction is a load
|
||
|
|
// using the register offset addressing mode.
|
||
|
|
def IsLoadRegOffsetOp : CheckOpcode<[PRFMroW, PRFMroX,
|
||
|
|
LDRBBroW, LDRBBroX,
|
||
|
|
LDRSBWroW, LDRSBWroX, LDRSBXroW, LDRSBXroX,
|
||
|
|
LDRHHroW, LDRHHroX,
|
||
|
|
LDRSHWroW, LDRSHWroX, LDRSHXroW, LDRSHXroX,
|
||
|
|
LDRWroW, LDRWroX,
|
||
|
|
LDRSWroW, LDRSWroX,
|
||
|
|
LDRXroW, LDRXroX,
|
||
|
|
LDRBroW, LDRBroX,
|
||
|
|
LDRHroW, LDRHroX,
|
||
|
|
LDRSroW, LDRSroX,
|
||
|
|
LDRDroW, LDRDroX,
|
||
|
|
LDRQroW, LDRQroX]>;
|
||
|
|
|
||
|
|
// Identify whether an instruction is a store
|
||
|
|
// using the register offset addressing mode.
|
||
|
|
def IsStoreRegOffsetOp : CheckOpcode<[STRBBroW, STRBBroX,
|
||
|
|
STRHHroW, STRHHroX,
|
||
|
|
STRWroW, STRWroX,
|
||
|
|
STRXroW, STRXroX,
|
||
|
|
STRBroW, STRBroX,
|
||
|
|
STRHroW, STRHroX,
|
||
|
|
STRSroW, STRSroX,
|
||
|
|
STRDroW, STRDroX,
|
||
|
|
STRQroW, STRQroX]>;
|
||
|
|
|
||
|
|
// Identify whether an instruction is a load or
|
||
|
|
// store using the register offset addressing mode.
|
||
|
|
def IsLoadStoreRegOffsetOp : CheckOpcode<!listconcat(IsLoadRegOffsetOp.ValidOpcodes,
|
||
|
|
IsStoreRegOffsetOp.ValidOpcodes)>;
|
||
|
|
|
||
|
|
// Target predicates.
|
||
|
|
|
||
|
|
// Identify an instruction that effectively transfers a register to another.
|
||
|
|
def IsCopyIdiomFn : TIIPredicate<"isCopyIdiom",
|
||
|
|
MCOpcodeSwitchStatement<
|
||
|
|
[// MOV {Rd, SP}, {SP, Rn} =>
|
||
|
|
// ADD {Rd, SP}, {SP, Rn}, #0
|
||
|
|
MCOpcodeSwitchCase<
|
||
|
|
[ADDWri, ADDXri],
|
||
|
|
MCReturnStatement<
|
||
|
|
CheckAll<
|
||
|
|
[CheckIsRegOperand<0>,
|
||
|
|
CheckIsRegOperand<1>,
|
||
|
|
CheckAny<
|
||
|
|
[CheckRegOperand<0, WSP>,
|
||
|
|
CheckRegOperand<0, SP>,
|
||
|
|
CheckRegOperand<1, WSP>,
|
||
|
|
CheckRegOperand<1, SP>]>,
|
||
|
|
CheckZeroOperand<2>]>>>,
|
||
|
|
// MOV Rd, Rm =>
|
||
|
|
// ORR Rd, ZR, Rm, LSL #0
|
||
|
|
MCOpcodeSwitchCase<
|
||
|
|
[ORRWrs, ORRXrs],
|
||
|
|
MCReturnStatement<
|
||
|
|
CheckAll<
|
||
|
|
[CheckIsRegOperand<1>,
|
||
|
|
CheckIsRegOperand<2>,
|
||
|
|
CheckAny<
|
||
|
|
[CheckRegOperand<1, WZR>,
|
||
|
|
CheckRegOperand<1, XZR>]>,
|
||
|
|
CheckShiftBy0]>>>],
|
||
|
|
MCReturnStatement<FalsePred>>>;
|
||
|
|
def IsCopyIdiomPred : MCSchedPredicate<IsCopyIdiomFn>;
|
||
|
|
|
||
|
|
// Identify arithmetic instructions with an extended register.
|
||
|
|
def RegExtendedFn : TIIPredicate<"hasExtendedReg",
|
||
|
|
MCOpcodeSwitchStatement<
|
||
|
|
[MCOpcodeSwitchCase<
|
||
|
|
IsArithExtOp.ValidOpcodes,
|
||
|
|
MCReturnStatement<
|
||
|
|
CheckNot<CheckZeroOperand<3>>>>],
|
||
|
|
MCReturnStatement<FalsePred>>>;
|
||
|
|
def RegExtendedPred : MCSchedPredicate<RegExtendedFn>;
|
||
|
|
|
||
|
|
// Identify arithmetic and logic instructions with a shifted register.
|
||
|
|
def RegShiftedFn : TIIPredicate<"hasShiftedReg",
|
||
|
|
MCOpcodeSwitchStatement<
|
||
|
|
[MCOpcodeSwitchCase<
|
||
|
|
IsArithLogicShiftOp.ValidOpcodes,
|
||
|
|
MCReturnStatement<
|
||
|
|
CheckNot<CheckZeroOperand<3>>>>],
|
||
|
|
MCReturnStatement<FalsePred>>>;
|
||
|
|
def RegShiftedPred : MCSchedPredicate<RegShiftedFn>;
|
||
|
|
|
||
|
|
// Identify a load or store using the register offset addressing mode
|
||
|
|
// with an extended or scaled register.
|
||
|
|
def ScaledIdxFn : TIIPredicate<"isScaledAddr",
|
||
|
|
MCOpcodeSwitchStatement<
|
||
|
|
[MCOpcodeSwitchCase<
|
||
|
|
IsLoadStoreRegOffsetOp.ValidOpcodes,
|
||
|
|
MCReturnStatement<
|
||
|
|
CheckAny<[CheckNot<CheckMemExtLSL>,
|
||
|
|
CheckMemScaled]>>>],
|
||
|
|
MCReturnStatement<FalsePred>>>;
|
||
|
|
def ScaledIdxPred : MCSchedPredicate<ScaledIdxFn>;
|
||
|
|
|
||
|
|
// Identify an instruction that effectively resets a FP register to zero.
|
||
|
|
def IsZeroFPIdiomFn : TIIPredicate<"isZeroFPIdiom",
|
||
|
|
MCOpcodeSwitchStatement<
|
||
|
|
[// MOVI Vd, #0
|
||
|
|
MCOpcodeSwitchCase<
|
||
|
|
[MOVIv8b_ns, MOVIv16b_ns,
|
||
|
|
MOVID, MOVIv2d_ns],
|
||
|
|
MCReturnStatement<CheckZeroOperand<1>>>,
|
||
|
|
// MOVI Vd, #0, LSL #0
|
||
|
|
MCOpcodeSwitchCase<
|
||
|
|
[MOVIv4i16, MOVIv8i16,
|
||
|
|
MOVIv2i32, MOVIv4i32],
|
||
|
|
MCReturnStatement<
|
||
|
|
CheckAll<
|
||
|
|
[CheckZeroOperand<1>,
|
||
|
|
CheckZeroOperand<2>]>>>],
|
||
|
|
MCReturnStatement<FalsePred>>>;
|
||
|
|
def IsZeroFPIdiomPred : MCSchedPredicate<IsZeroFPIdiomFn>;
|
||
|
|
|
||
|
|
// Identify an instruction that effectively resets a GP register to zero.
|
||
|
|
def IsZeroIdiomFn : TIIPredicate<"isZeroIdiom",
|
||
|
|
MCOpcodeSwitchStatement<
|
||
|
|
[// ORR Rd, ZR, #0
|
||
|
|
MCOpcodeSwitchCase<
|
||
|
|
[ORRWri, ORRXri],
|
||
|
|
MCReturnStatement<
|
||
|
|
CheckAll<
|
||
|
|
[CheckIsRegOperand<1>,
|
||
|
|
CheckAny<
|
||
|
|
[CheckRegOperand<1, WZR>,
|
||
|
|
CheckRegOperand<1, XZR>]>,
|
||
|
|
CheckZeroOperand<2>]>>>],
|
||
|
|
MCReturnStatement<FalsePred>>>;
|
||
|
|
def IsZeroIdiomPred : MCSchedPredicate<IsZeroIdiomFn>;
|