247 lines
8.7 KiB
C++
247 lines
8.7 KiB
C++
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//===- LiveRangeShrink.cpp - Move instructions to shrink live range -------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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///===---------------------------------------------------------------------===//
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///
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/// \file
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/// This pass moves instructions close to the definition of its operands to
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/// shrink live range of the def instruction. The code motion is limited within
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/// the basic block. The moved instruction should have 1 def, and more than one
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/// uses, all of which are the only use of the def.
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///
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///===---------------------------------------------------------------------===//
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/iterator_range.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include <iterator>
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#include <utility>
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using namespace llvm;
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#define DEBUG_TYPE "lrshrink"
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STATISTIC(NumInstrsHoistedToShrinkLiveRange,
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"Number of insructions hoisted to shrink live range.");
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namespace {
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class LiveRangeShrink : public MachineFunctionPass {
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public:
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static char ID;
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LiveRangeShrink() : MachineFunctionPass(ID) {
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initializeLiveRangeShrinkPass(*PassRegistry::getPassRegistry());
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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StringRef getPassName() const override { return "Live Range Shrink"; }
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bool runOnMachineFunction(MachineFunction &MF) override;
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};
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} // end anonymous namespace
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char LiveRangeShrink::ID = 0;
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char &llvm::LiveRangeShrinkID = LiveRangeShrink::ID;
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INITIALIZE_PASS(LiveRangeShrink, "lrshrink", "Live Range Shrink Pass", false,
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false)
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using InstOrderMap = DenseMap<MachineInstr *, unsigned>;
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/// Returns \p New if it's dominated by \p Old, otherwise return \p Old.
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/// \p M maintains a map from instruction to its dominating order that satisfies
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/// M[A] > M[B] guarantees that A is dominated by B.
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/// If \p New is not in \p M, return \p Old. Otherwise if \p Old is null, return
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/// \p New.
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static MachineInstr *FindDominatedInstruction(MachineInstr &New,
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MachineInstr *Old,
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const InstOrderMap &M) {
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auto NewIter = M.find(&New);
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if (NewIter == M.end())
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return Old;
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if (Old == nullptr)
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return &New;
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unsigned OrderOld = M.find(Old)->second;
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unsigned OrderNew = NewIter->second;
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if (OrderOld != OrderNew)
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return OrderOld < OrderNew ? &New : Old;
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// OrderOld == OrderNew, we need to iterate down from Old to see if it
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// can reach New, if yes, New is dominated by Old.
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for (MachineInstr *I = Old->getNextNode(); M.find(I)->second == OrderNew;
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I = I->getNextNode())
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if (I == &New)
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return &New;
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return Old;
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}
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/// Builds Instruction to its dominating order number map \p M by traversing
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/// from instruction \p Start.
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static void BuildInstOrderMap(MachineBasicBlock::iterator Start,
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InstOrderMap &M) {
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M.clear();
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unsigned i = 0;
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for (MachineInstr &I : make_range(Start, Start->getParent()->end()))
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M[&I] = i++;
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}
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bool LiveRangeShrink::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(MF.getFunction()))
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return false;
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MachineRegisterInfo &MRI = MF.getRegInfo();
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LLVM_DEBUG(dbgs() << "**** Analysing " << MF.getName() << '\n');
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InstOrderMap IOM;
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// Map from register to instruction order (value of IOM) where the
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// register is used last. When moving instructions up, we need to
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// make sure all its defs (including dead def) will not cross its
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// last use when moving up.
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DenseMap<unsigned, std::pair<unsigned, MachineInstr *>> UseMap;
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for (MachineBasicBlock &MBB : MF) {
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if (MBB.empty())
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continue;
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bool SawStore = false;
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BuildInstOrderMap(MBB.begin(), IOM);
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UseMap.clear();
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for (MachineBasicBlock::iterator Next = MBB.begin(); Next != MBB.end();) {
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MachineInstr &MI = *Next;
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++Next;
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if (MI.isPHI() || MI.isDebugInstr())
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continue;
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if (MI.mayStore())
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SawStore = true;
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unsigned CurrentOrder = IOM[&MI];
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unsigned Barrier = 0;
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MachineInstr *BarrierMI = nullptr;
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for (const MachineOperand &MO : MI.operands()) {
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if (!MO.isReg() || MO.isDebug())
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continue;
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if (MO.isUse())
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UseMap[MO.getReg()] = std::make_pair(CurrentOrder, &MI);
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else if (MO.isDead() && UseMap.count(MO.getReg()))
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// Barrier is the last instruction where MO get used. MI should not
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// be moved above Barrier.
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if (Barrier < UseMap[MO.getReg()].first) {
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Barrier = UseMap[MO.getReg()].first;
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BarrierMI = UseMap[MO.getReg()].second;
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}
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}
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if (!MI.isSafeToMove(nullptr, SawStore)) {
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// If MI has side effects, it should become a barrier for code motion.
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// IOM is rebuild from the next instruction to prevent later
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// instructions from being moved before this MI.
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if (MI.hasUnmodeledSideEffects() && !MI.isPseudoProbe() &&
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Next != MBB.end()) {
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BuildInstOrderMap(Next, IOM);
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SawStore = false;
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}
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continue;
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}
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const MachineOperand *DefMO = nullptr;
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MachineInstr *Insert = nullptr;
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// Number of live-ranges that will be shortened. We do not count
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// live-ranges that are defined by a COPY as it could be coalesced later.
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unsigned NumEligibleUse = 0;
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for (const MachineOperand &MO : MI.operands()) {
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if (!MO.isReg() || MO.isDead() || MO.isDebug())
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continue;
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Register Reg = MO.getReg();
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// Do not move the instruction if it def/uses a physical register,
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// unless it is a constant physical register or a noreg.
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if (!Register::isVirtualRegister(Reg)) {
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if (!Reg || MRI.isConstantPhysReg(Reg))
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continue;
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Insert = nullptr;
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break;
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}
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if (MO.isDef()) {
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// Do not move if there is more than one def.
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if (DefMO) {
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Insert = nullptr;
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break;
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}
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DefMO = &MO;
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} else if (MRI.hasOneNonDBGUse(Reg) && MRI.hasOneDef(Reg) && DefMO &&
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MRI.getRegClass(DefMO->getReg()) ==
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MRI.getRegClass(MO.getReg())) {
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// The heuristic does not handle different register classes yet
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// (registers of different sizes, looser/tighter constraints). This
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// is because it needs more accurate model to handle register
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// pressure correctly.
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MachineInstr &DefInstr = *MRI.def_instr_begin(Reg);
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if (!DefInstr.isCopy())
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NumEligibleUse++;
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Insert = FindDominatedInstruction(DefInstr, Insert, IOM);
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} else {
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Insert = nullptr;
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break;
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}
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}
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// If Barrier equals IOM[I], traverse forward to find if BarrierMI is
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// after Insert, if yes, then we should not hoist.
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for (MachineInstr *I = Insert; I && IOM[I] == Barrier;
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I = I->getNextNode())
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if (I == BarrierMI) {
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Insert = nullptr;
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break;
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}
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// Move the instruction when # of shrunk live range > 1.
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if (DefMO && Insert && NumEligibleUse > 1 && Barrier <= IOM[Insert]) {
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MachineBasicBlock::iterator I = std::next(Insert->getIterator());
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// Skip all the PHI and debug instructions.
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while (I != MBB.end() && (I->isPHI() || I->isDebugInstr()))
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I = std::next(I);
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if (I == MI.getIterator())
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continue;
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// Update the dominator order to be the same as the insertion point.
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// We do this to maintain a non-decreasing order without need to update
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// all instruction orders after the insertion point.
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unsigned NewOrder = IOM[&*I];
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IOM[&MI] = NewOrder;
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NumInstrsHoistedToShrinkLiveRange++;
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// Find MI's debug value following MI.
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MachineBasicBlock::iterator EndIter = std::next(MI.getIterator());
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if (MI.getOperand(0).isReg())
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for (; EndIter != MBB.end() && EndIter->isDebugValue() &&
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EndIter->getDebugOperandForReg(MI.getOperand(0).getReg());
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++EndIter, ++Next)
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IOM[&*EndIter] = NewOrder;
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MBB.splice(I, &MBB, MI.getIterator(), EndIter);
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}
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}
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}
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return false;
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}
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