490 lines
19 KiB
C
490 lines
19 KiB
C
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//===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the TargetMachine and LLVMTargetMachine classes.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_TARGETMACHINE_H
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#define LLVM_TARGET_TARGETMACHINE_H
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/PassManager.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/CodeGen.h"
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#include "llvm/Support/Error.h"
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#include "llvm/Target/CGPassBuilderOption.h"
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#include "llvm/Target/TargetOptions.h"
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#include <string>
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namespace llvm {
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class AAManager;
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template <typename IRUnitT, typename AnalysisManagerT, typename... ExtraArgTs>
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class PassManager;
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using ModulePassManager = PassManager<Module>;
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class Function;
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class GlobalValue;
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class MachineFunctionPassManager;
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class MachineFunctionAnalysisManager;
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class MachineModuleInfoWrapperPass;
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class Mangler;
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class MCAsmInfo;
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class MCContext;
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class MCInstrInfo;
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class MCRegisterInfo;
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class MCStreamer;
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class MCSubtargetInfo;
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class MCSymbol;
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class raw_pwrite_stream;
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class PassBuilder;
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class PassManagerBuilder;
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struct PerFunctionMIParsingState;
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class SMDiagnostic;
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class SMRange;
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class Target;
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class TargetIntrinsicInfo;
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class TargetIRAnalysis;
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class TargetTransformInfo;
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class TargetLoweringObjectFile;
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class TargetPassConfig;
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class TargetSubtargetInfo;
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// The old pass manager infrastructure is hidden in a legacy namespace now.
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namespace legacy {
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class PassManagerBase;
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}
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using legacy::PassManagerBase;
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namespace yaml {
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struct MachineFunctionInfo;
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}
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//===----------------------------------------------------------------------===//
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///
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/// Primary interface to the complete machine description for the target
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/// machine. All target-specific information should be accessible through this
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/// interface.
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///
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class TargetMachine {
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protected: // Can only create subclasses.
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TargetMachine(const Target &T, StringRef DataLayoutString,
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const Triple &TargetTriple, StringRef CPU, StringRef FS,
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const TargetOptions &Options);
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/// The Target that this machine was created for.
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const Target &TheTarget;
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/// DataLayout for the target: keep ABI type size and alignment.
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///
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/// The DataLayout is created based on the string representation provided
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/// during construction. It is kept here only to avoid reparsing the string
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/// but should not really be used during compilation, because it has an
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/// internal cache that is context specific.
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const DataLayout DL;
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/// Triple string, CPU name, and target feature strings the TargetMachine
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/// instance is created with.
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Triple TargetTriple;
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std::string TargetCPU;
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std::string TargetFS;
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Reloc::Model RM = Reloc::Static;
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CodeModel::Model CMModel = CodeModel::Small;
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CodeGenOpt::Level OptLevel = CodeGenOpt::Default;
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/// Contains target specific asm information.
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std::unique_ptr<const MCAsmInfo> AsmInfo;
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std::unique_ptr<const MCRegisterInfo> MRI;
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std::unique_ptr<const MCInstrInfo> MII;
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std::unique_ptr<const MCSubtargetInfo> STI;
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unsigned RequireStructuredCFG : 1;
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unsigned O0WantsFastISel : 1;
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public:
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const TargetOptions DefaultOptions;
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mutable TargetOptions Options;
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TargetMachine(const TargetMachine &) = delete;
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void operator=(const TargetMachine &) = delete;
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virtual ~TargetMachine();
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const Target &getTarget() const { return TheTarget; }
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const Triple &getTargetTriple() const { return TargetTriple; }
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StringRef getTargetCPU() const { return TargetCPU; }
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StringRef getTargetFeatureString() const { return TargetFS; }
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void setTargetFeatureString(StringRef FS) { TargetFS = std::string(FS); }
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/// Virtual method implemented by subclasses that returns a reference to that
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/// target's TargetSubtargetInfo-derived member variable.
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virtual const TargetSubtargetInfo *getSubtargetImpl(const Function &) const {
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return nullptr;
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}
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virtual TargetLoweringObjectFile *getObjFileLowering() const {
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return nullptr;
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}
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/// Allocate and return a default initialized instance of the YAML
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/// representation for the MachineFunctionInfo.
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virtual yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const {
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return nullptr;
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}
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/// Allocate and initialize an instance of the YAML representation of the
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/// MachineFunctionInfo.
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virtual yaml::MachineFunctionInfo *
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convertFuncInfoToYAML(const MachineFunction &MF) const {
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return nullptr;
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}
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/// Parse out the target's MachineFunctionInfo from the YAML reprsentation.
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virtual bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,
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PerFunctionMIParsingState &PFS,
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SMDiagnostic &Error,
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SMRange &SourceRange) const {
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return false;
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}
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/// This method returns a pointer to the specified type of
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/// TargetSubtargetInfo. In debug builds, it verifies that the object being
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/// returned is of the correct type.
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template <typename STC> const STC &getSubtarget(const Function &F) const {
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return *static_cast<const STC*>(getSubtargetImpl(F));
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}
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/// Create a DataLayout.
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const DataLayout createDataLayout() const { return DL; }
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/// Test if a DataLayout if compatible with the CodeGen for this target.
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///
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/// The LLVM Module owns a DataLayout that is used for the target independent
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/// optimizations and code generation. This hook provides a target specific
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/// check on the validity of this DataLayout.
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bool isCompatibleDataLayout(const DataLayout &Candidate) const {
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return DL == Candidate;
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}
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/// Get the pointer size for this target.
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///
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/// This is the only time the DataLayout in the TargetMachine is used.
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unsigned getPointerSize(unsigned AS) const {
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return DL.getPointerSize(AS);
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}
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unsigned getPointerSizeInBits(unsigned AS) const {
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return DL.getPointerSizeInBits(AS);
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}
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unsigned getProgramPointerSize() const {
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return DL.getPointerSize(DL.getProgramAddressSpace());
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}
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unsigned getAllocaPointerSize() const {
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return DL.getPointerSize(DL.getAllocaAddrSpace());
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}
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/// Reset the target options based on the function's attributes.
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// FIXME: Remove TargetOptions that affect per-function code generation
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// from TargetMachine.
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void resetTargetOptions(const Function &F) const;
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/// Return target specific asm information.
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const MCAsmInfo *getMCAsmInfo() const { return AsmInfo.get(); }
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const MCRegisterInfo *getMCRegisterInfo() const { return MRI.get(); }
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const MCInstrInfo *getMCInstrInfo() const { return MII.get(); }
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const MCSubtargetInfo *getMCSubtargetInfo() const { return STI.get(); }
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/// If intrinsic information is available, return it. If not, return null.
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virtual const TargetIntrinsicInfo *getIntrinsicInfo() const {
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return nullptr;
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}
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bool requiresStructuredCFG() const { return RequireStructuredCFG; }
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void setRequiresStructuredCFG(bool Value) { RequireStructuredCFG = Value; }
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/// Returns the code generation relocation model. The choices are static, PIC,
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/// and dynamic-no-pic, and target default.
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Reloc::Model getRelocationModel() const;
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/// Returns the code model. The choices are small, kernel, medium, large, and
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/// target default.
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CodeModel::Model getCodeModel() const;
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bool isPositionIndependent() const;
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bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const;
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/// Returns true if this target uses emulated TLS.
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bool useEmulatedTLS() const;
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/// Returns the TLS model which should be used for the given global variable.
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TLSModel::Model getTLSModel(const GlobalValue *GV) const;
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/// Returns the optimization level: None, Less, Default, or Aggressive.
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CodeGenOpt::Level getOptLevel() const;
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/// Overrides the optimization level.
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void setOptLevel(CodeGenOpt::Level Level);
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void setFastISel(bool Enable) { Options.EnableFastISel = Enable; }
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bool getO0WantsFastISel() { return O0WantsFastISel; }
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void setO0WantsFastISel(bool Enable) { O0WantsFastISel = Enable; }
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void setGlobalISel(bool Enable) { Options.EnableGlobalISel = Enable; }
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void setGlobalISelAbort(GlobalISelAbortMode Mode) {
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Options.GlobalISelAbort = Mode;
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}
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void setMachineOutliner(bool Enable) {
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Options.EnableMachineOutliner = Enable;
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}
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void setSupportsDefaultOutlining(bool Enable) {
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Options.SupportsDefaultOutlining = Enable;
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}
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void setSupportsDebugEntryValues(bool Enable) {
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Options.SupportsDebugEntryValues = Enable;
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}
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bool getAIXExtendedAltivecABI() const {
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return Options.EnableAIXExtendedAltivecABI;
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}
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bool getUniqueSectionNames() const { return Options.UniqueSectionNames; }
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/// Return true if unique basic block section names must be generated.
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bool getUniqueBasicBlockSectionNames() const {
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return Options.UniqueBasicBlockSectionNames;
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}
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/// Return true if data objects should be emitted into their own section,
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/// corresponds to -fdata-sections.
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bool getDataSections() const {
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return Options.DataSections;
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}
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/// Return true if functions should be emitted into their own section,
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/// corresponding to -ffunction-sections.
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bool getFunctionSections() const {
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return Options.FunctionSections;
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}
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/// Return true if visibility attribute should not be emitted in XCOFF,
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/// corresponding to -mignore-xcoff-visibility.
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bool getIgnoreXCOFFVisibility() const {
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return Options.IgnoreXCOFFVisibility;
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}
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/// Return true if XCOFF traceback table should be emitted,
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/// corresponding to -xcoff-traceback-table.
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bool getXCOFFTracebackTable() const { return Options.XCOFFTracebackTable; }
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/// If basic blocks should be emitted into their own section,
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/// corresponding to -fbasic-block-sections.
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llvm::BasicBlockSection getBBSectionsType() const {
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return Options.BBSections;
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}
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/// Get the list of functions and basic block ids that need unique sections.
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const MemoryBuffer *getBBSectionsFuncListBuf() const {
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return Options.BBSectionsFuncListBuf.get();
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}
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/// Returns true if a cast between SrcAS and DestAS is a noop.
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virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
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return false;
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}
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/// If the specified generic pointer could be assumed as a pointer to a
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/// specific address space, return that address space.
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///
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/// Under offloading programming, the offloading target may be passed with
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/// values only prepared on the host side and could assume certain
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/// properties.
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virtual unsigned getAssumedAddrSpace(const Value *V) const { return -1; }
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/// Get a \c TargetIRAnalysis appropriate for the target.
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///
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/// This is used to construct the new pass manager's target IR analysis pass,
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/// set up appropriately for this target machine. Even the old pass manager
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/// uses this to answer queries about the IR.
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TargetIRAnalysis getTargetIRAnalysis();
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/// Return a TargetTransformInfo for a given function.
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///
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/// The returned TargetTransformInfo is specialized to the subtarget
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/// corresponding to \p F.
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virtual TargetTransformInfo getTargetTransformInfo(const Function &F);
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/// Allow the target to modify the pass manager, e.g. by calling
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/// PassManagerBuilder::addExtension.
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virtual void adjustPassManager(PassManagerBuilder &) {}
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/// Allow the target to modify the pass pipeline with New Pass Manager
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/// (similar to adjustPassManager for Legacy Pass manager).
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virtual void registerPassBuilderCallbacks(PassBuilder &,
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bool DebugPassManager) {}
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/// Allow the target to register alias analyses with the AAManager for use
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/// with the new pass manager. Only affects the "default" AAManager.
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virtual void registerDefaultAliasAnalyses(AAManager &) {}
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/// Add passes to the specified pass manager to get the specified file
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/// emitted. Typically this will involve several steps of code generation.
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/// This method should return true if emission of this file type is not
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/// supported, or false on success.
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/// \p MMIWP is an optional parameter that, if set to non-nullptr,
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/// will be used to set the MachineModuloInfo for this PM.
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virtual bool
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addPassesToEmitFile(PassManagerBase &, raw_pwrite_stream &,
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raw_pwrite_stream *, CodeGenFileType,
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bool /*DisableVerify*/ = true,
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MachineModuleInfoWrapperPass *MMIWP = nullptr) {
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return true;
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}
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/// Add passes to the specified pass manager to get machine code emitted with
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/// the MCJIT. This method returns true if machine code is not supported. It
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/// fills the MCContext Ctx pointer which can be used to build custom
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/// MCStreamer.
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///
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virtual bool addPassesToEmitMC(PassManagerBase &, MCContext *&,
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raw_pwrite_stream &,
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bool /*DisableVerify*/ = true) {
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return true;
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}
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/// True if subtarget inserts the final scheduling pass on its own.
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///
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/// Branch relaxation, which must happen after block placement, can
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/// on some targets (e.g. SystemZ) expose additional post-RA
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/// scheduling opportunities.
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virtual bool targetSchedulesPostRAScheduling() const { return false; };
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void getNameWithPrefix(SmallVectorImpl<char> &Name, const GlobalValue *GV,
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Mangler &Mang, bool MayAlwaysUsePrivate = false) const;
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MCSymbol *getSymbol(const GlobalValue *GV) const;
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||
|
|
/// The integer bit size to use for SjLj based exception handling.
|
||
|
|
static constexpr unsigned DefaultSjLjDataSize = 32;
|
||
|
|
virtual unsigned getSjLjDataSize() const { return DefaultSjLjDataSize; }
|
||
|
|
|
||
|
|
static std::pair<int, int> parseBinutilsVersion(StringRef Version);
|
||
|
|
};
|
||
|
|
|
||
|
|
/// This class describes a target machine that is implemented with the LLVM
|
||
|
|
/// target-independent code generator.
|
||
|
|
///
|
||
|
|
class LLVMTargetMachine : public TargetMachine {
|
||
|
|
protected: // Can only create subclasses.
|
||
|
|
LLVMTargetMachine(const Target &T, StringRef DataLayoutString,
|
||
|
|
const Triple &TT, StringRef CPU, StringRef FS,
|
||
|
|
const TargetOptions &Options, Reloc::Model RM,
|
||
|
|
CodeModel::Model CM, CodeGenOpt::Level OL);
|
||
|
|
|
||
|
|
void initAsmInfo();
|
||
|
|
|
||
|
|
public:
|
||
|
|
/// Get a TargetTransformInfo implementation for the target.
|
||
|
|
///
|
||
|
|
/// The TTI returned uses the common code generator to answer queries about
|
||
|
|
/// the IR.
|
||
|
|
TargetTransformInfo getTargetTransformInfo(const Function &F) override;
|
||
|
|
|
||
|
|
/// Create a pass configuration object to be used by addPassToEmitX methods
|
||
|
|
/// for generating a pipeline of CodeGen passes.
|
||
|
|
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
|
||
|
|
|
||
|
|
/// Add passes to the specified pass manager to get the specified file
|
||
|
|
/// emitted. Typically this will involve several steps of code generation.
|
||
|
|
/// \p MMIWP is an optional parameter that, if set to non-nullptr,
|
||
|
|
/// will be used to set the MachineModuloInfo for this PM.
|
||
|
|
bool
|
||
|
|
addPassesToEmitFile(PassManagerBase &PM, raw_pwrite_stream &Out,
|
||
|
|
raw_pwrite_stream *DwoOut, CodeGenFileType FileType,
|
||
|
|
bool DisableVerify = true,
|
||
|
|
MachineModuleInfoWrapperPass *MMIWP = nullptr) override;
|
||
|
|
|
||
|
|
virtual Error buildCodeGenPipeline(ModulePassManager &,
|
||
|
|
MachineFunctionPassManager &,
|
||
|
|
MachineFunctionAnalysisManager &,
|
||
|
|
raw_pwrite_stream &, raw_pwrite_stream *,
|
||
|
|
CodeGenFileType, CGPassBuilderOption,
|
||
|
|
PassInstrumentationCallbacks *) {
|
||
|
|
return make_error<StringError>("buildCodeGenPipeline is not overriden",
|
||
|
|
inconvertibleErrorCode());
|
||
|
|
}
|
||
|
|
|
||
|
|
virtual std::pair<StringRef, bool> getPassNameFromLegacyName(StringRef) {
|
||
|
|
llvm_unreachable(
|
||
|
|
"getPassNameFromLegacyName parseMIRPipeline is not overriden");
|
||
|
|
}
|
||
|
|
|
||
|
|
/// Add passes to the specified pass manager to get machine code emitted with
|
||
|
|
/// the MCJIT. This method returns true if machine code is not supported. It
|
||
|
|
/// fills the MCContext Ctx pointer which can be used to build custom
|
||
|
|
/// MCStreamer.
|
||
|
|
bool addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx,
|
||
|
|
raw_pwrite_stream &Out,
|
||
|
|
bool DisableVerify = true) override;
|
||
|
|
|
||
|
|
/// Returns true if the target is expected to pass all machine verifier
|
||
|
|
/// checks. This is a stopgap measure to fix targets one by one. We will
|
||
|
|
/// remove this at some point and always enable the verifier when
|
||
|
|
/// EXPENSIVE_CHECKS is enabled.
|
||
|
|
virtual bool isMachineVerifierClean() const { return true; }
|
||
|
|
|
||
|
|
/// Adds an AsmPrinter pass to the pipeline that prints assembly or
|
||
|
|
/// machine code from the MI representation.
|
||
|
|
bool addAsmPrinter(PassManagerBase &PM, raw_pwrite_stream &Out,
|
||
|
|
raw_pwrite_stream *DwoOut, CodeGenFileType FileType,
|
||
|
|
MCContext &Context);
|
||
|
|
|
||
|
|
Expected<std::unique_ptr<MCStreamer>>
|
||
|
|
createMCStreamer(raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut,
|
||
|
|
CodeGenFileType FileType, MCContext &Ctx);
|
||
|
|
|
||
|
|
/// True if the target uses physical regs (as nearly all targets do). False
|
||
|
|
/// for stack machines such as WebAssembly and other virtual-register
|
||
|
|
/// machines. If true, all vregs must be allocated before PEI. If false, then
|
||
|
|
/// callee-save register spilling and scavenging are not needed or used. If
|
||
|
|
/// false, implicitly defined registers will still be assumed to be physical
|
||
|
|
/// registers, except that variadic defs will be allocated vregs.
|
||
|
|
virtual bool usesPhysRegsForValues() const { return true; }
|
||
|
|
|
||
|
|
/// True if the target wants to use interprocedural register allocation by
|
||
|
|
/// default. The -enable-ipra flag can be used to override this.
|
||
|
|
virtual bool useIPRA() const {
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
};
|
||
|
|
|
||
|
|
/// Helper method for getting the code model, returning Default if
|
||
|
|
/// CM does not have a value. The tiny and kernel models will produce
|
||
|
|
/// an error, so targets that support them or require more complex codemodel
|
||
|
|
/// selection logic should implement and call their own getEffectiveCodeModel.
|
||
|
|
inline CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM,
|
||
|
|
CodeModel::Model Default) {
|
||
|
|
if (CM) {
|
||
|
|
// By default, targets do not support the tiny and kernel models.
|
||
|
|
if (*CM == CodeModel::Tiny)
|
||
|
|
report_fatal_error("Target does not support the tiny CodeModel", false);
|
||
|
|
if (*CM == CodeModel::Kernel)
|
||
|
|
report_fatal_error("Target does not support the kernel CodeModel", false);
|
||
|
|
return *CM;
|
||
|
|
}
|
||
|
|
return Default;
|
||
|
|
}
|
||
|
|
|
||
|
|
} // end namespace llvm
|
||
|
|
|
||
|
|
#endif // LLVM_TARGET_TARGETMACHINE_H
|