238 lines
9.0 KiB
C
238 lines
9.0 KiB
C
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//===- llvm/MC/MCInstrItineraries.h - Scheduling ----------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the structures used for instruction
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// itineraries, stages, and operand reads/writes. This is used by
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// schedulers to determine instruction stages and latencies.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_MC_MCINSTRITINERARIES_H
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#define LLVM_MC_MCINSTRITINERARIES_H
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#include "llvm/MC/MCSchedule.h"
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#include <algorithm>
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namespace llvm {
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//===----------------------------------------------------------------------===//
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/// These values represent a non-pipelined step in
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/// the execution of an instruction. Cycles represents the number of
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/// discrete time slots needed to complete the stage. Units represent
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/// the choice of functional units that can be used to complete the
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/// stage. Eg. IntUnit1, IntUnit2. NextCycles indicates how many
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/// cycles should elapse from the start of this stage to the start of
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/// the next stage in the itinerary. A value of -1 indicates that the
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/// next stage should start immediately after the current one.
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/// For example:
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///
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/// { 1, x, -1 }
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/// indicates that the stage occupies FU x for 1 cycle and that
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/// the next stage starts immediately after this one.
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///
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/// { 2, x|y, 1 }
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/// indicates that the stage occupies either FU x or FU y for 2
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/// consecutive cycles and that the next stage starts one cycle
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/// after this stage starts. That is, the stage requirements
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/// overlap in time.
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///
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/// { 1, x, 0 }
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/// indicates that the stage occupies FU x for 1 cycle and that
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/// the next stage starts in this same cycle. This can be used to
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/// indicate that the instruction requires multiple stages at the
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/// same time.
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///
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/// FU reservation can be of two different kinds:
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/// - FUs which instruction actually requires
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/// - FUs which instruction just reserves. Reserved unit is not available for
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/// execution of other instruction. However, several instructions can reserve
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/// the same unit several times.
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/// Such two types of units reservation is used to model instruction domain
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/// change stalls, FUs using the same resource (e.g. same register file), etc.
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struct InstrStage {
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enum ReservationKinds {
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Required = 0,
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Reserved = 1
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};
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/// Bitmask representing a set of functional units.
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typedef uint64_t FuncUnits;
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unsigned Cycles_; ///< Length of stage in machine cycles
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FuncUnits Units_; ///< Choice of functional units
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int NextCycles_; ///< Number of machine cycles to next stage
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ReservationKinds Kind_; ///< Kind of the FU reservation
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/// Returns the number of cycles the stage is occupied.
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unsigned getCycles() const {
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return Cycles_;
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}
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/// Returns the choice of FUs.
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FuncUnits getUnits() const {
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return Units_;
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}
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ReservationKinds getReservationKind() const {
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return Kind_;
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}
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/// Returns the number of cycles from the start of this stage to the
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/// start of the next stage in the itinerary
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unsigned getNextCycles() const {
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return (NextCycles_ >= 0) ? (unsigned)NextCycles_ : Cycles_;
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}
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};
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//===----------------------------------------------------------------------===//
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/// An itinerary represents the scheduling information for an instruction.
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/// This includes a set of stages occupied by the instruction and the pipeline
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/// cycle in which operands are read and written.
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///
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struct InstrItinerary {
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int16_t NumMicroOps; ///< # of micro-ops, -1 means it's variable
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uint16_t FirstStage; ///< Index of first stage in itinerary
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uint16_t LastStage; ///< Index of last + 1 stage in itinerary
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uint16_t FirstOperandCycle; ///< Index of first operand rd/wr
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uint16_t LastOperandCycle; ///< Index of last + 1 operand rd/wr
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};
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//===----------------------------------------------------------------------===//
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/// Itinerary data supplied by a subtarget to be used by a target.
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///
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class InstrItineraryData {
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public:
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MCSchedModel SchedModel =
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MCSchedModel::GetDefaultSchedModel(); ///< Basic machine properties.
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const InstrStage *Stages = nullptr; ///< Array of stages selected
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const unsigned *OperandCycles = nullptr; ///< Array of operand cycles selected
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const unsigned *Forwardings = nullptr; ///< Array of pipeline forwarding paths
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const InstrItinerary *Itineraries =
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nullptr; ///< Array of itineraries selected
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InstrItineraryData() = default;
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InstrItineraryData(const MCSchedModel &SM, const InstrStage *S,
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const unsigned *OS, const unsigned *F)
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: SchedModel(SM), Stages(S), OperandCycles(OS), Forwardings(F),
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Itineraries(SchedModel.InstrItineraries) {}
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/// Returns true if there are no itineraries.
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bool isEmpty() const { return Itineraries == nullptr; }
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/// Returns true if the index is for the end marker itinerary.
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bool isEndMarker(unsigned ItinClassIndx) const {
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return ((Itineraries[ItinClassIndx].FirstStage == UINT16_MAX) &&
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(Itineraries[ItinClassIndx].LastStage == UINT16_MAX));
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}
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/// Return the first stage of the itinerary.
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const InstrStage *beginStage(unsigned ItinClassIndx) const {
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unsigned StageIdx = Itineraries[ItinClassIndx].FirstStage;
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return Stages + StageIdx;
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}
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/// Return the last+1 stage of the itinerary.
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const InstrStage *endStage(unsigned ItinClassIndx) const {
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unsigned StageIdx = Itineraries[ItinClassIndx].LastStage;
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return Stages + StageIdx;
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}
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/// Return the total stage latency of the given class. The latency is
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/// the maximum completion time for any stage in the itinerary. If no stages
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/// exist, it defaults to one cycle.
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unsigned getStageLatency(unsigned ItinClassIndx) const {
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// If the target doesn't provide itinerary information, use a simple
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// non-zero default value for all instructions.
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if (isEmpty())
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return 1;
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// Calculate the maximum completion time for any stage.
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unsigned Latency = 0, StartCycle = 0;
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for (const InstrStage *IS = beginStage(ItinClassIndx),
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*E = endStage(ItinClassIndx); IS != E; ++IS) {
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Latency = std::max(Latency, StartCycle + IS->getCycles());
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StartCycle += IS->getNextCycles();
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}
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return Latency;
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}
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/// Return the cycle for the given class and operand. Return -1 if no
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/// cycle is specified for the operand.
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int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const {
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if (isEmpty())
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return -1;
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unsigned FirstIdx = Itineraries[ItinClassIndx].FirstOperandCycle;
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unsigned LastIdx = Itineraries[ItinClassIndx].LastOperandCycle;
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if ((FirstIdx + OperandIdx) >= LastIdx)
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return -1;
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return (int)OperandCycles[FirstIdx + OperandIdx];
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}
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/// Return true if there is a pipeline forwarding between instructions
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/// of itinerary classes DefClass and UseClasses so that value produced by an
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/// instruction of itinerary class DefClass, operand index DefIdx can be
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/// bypassed when it's read by an instruction of itinerary class UseClass,
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/// operand index UseIdx.
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bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx,
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unsigned UseClass, unsigned UseIdx) const {
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unsigned FirstDefIdx = Itineraries[DefClass].FirstOperandCycle;
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unsigned LastDefIdx = Itineraries[DefClass].LastOperandCycle;
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if ((FirstDefIdx + DefIdx) >= LastDefIdx)
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return false;
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if (Forwardings[FirstDefIdx + DefIdx] == 0)
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return false;
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unsigned FirstUseIdx = Itineraries[UseClass].FirstOperandCycle;
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unsigned LastUseIdx = Itineraries[UseClass].LastOperandCycle;
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if ((FirstUseIdx + UseIdx) >= LastUseIdx)
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return false;
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return Forwardings[FirstDefIdx + DefIdx] ==
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Forwardings[FirstUseIdx + UseIdx];
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}
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/// Compute and return the use operand latency of a given itinerary
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/// class and operand index if the value is produced by an instruction of the
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/// specified itinerary class and def operand index.
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int getOperandLatency(unsigned DefClass, unsigned DefIdx,
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unsigned UseClass, unsigned UseIdx) const {
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if (isEmpty())
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return -1;
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int DefCycle = getOperandCycle(DefClass, DefIdx);
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if (DefCycle == -1)
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return -1;
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int UseCycle = getOperandCycle(UseClass, UseIdx);
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if (UseCycle == -1)
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return -1;
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UseCycle = DefCycle - UseCycle + 1;
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if (UseCycle > 0 &&
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hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx))
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// FIXME: This assumes one cycle benefit for every pipeline forwarding.
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--UseCycle;
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return UseCycle;
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}
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/// Return the number of micro-ops that the given class decodes to.
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/// Return -1 for classes that require dynamic lookup via TargetInstrInfo.
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int getNumMicroOps(unsigned ItinClassIndx) const {
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if (isEmpty())
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return 1;
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return Itineraries[ItinClassIndx].NumMicroOps;
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}
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};
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} // end namespace llvm
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#endif // LLVM_MC_MCINSTRITINERARIES_H
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