581 lines
18 KiB
C
581 lines
18 KiB
C
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: %clang_cc1 -ffixed-point -triple x86_64-unknown-linux-gnu -S -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,SIGNED
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// RUN: %clang_cc1 -ffixed-point -triple x86_64-unknown-linux-gnu -fpadding-on-unsigned-fixed-point -S -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,UNSIGNED
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short _Accum sa;
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_Accum a;
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long _Accum la;
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short _Fract sf;
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_Fract f;
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long _Fract lf;
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unsigned short _Accum usa;
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unsigned _Accum ua;
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unsigned long _Accum ula;
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unsigned short _Fract usf;
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unsigned _Fract uf;
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unsigned long _Fract ulf;
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_Sat short _Accum sa_sat;
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_Sat _Accum a_sat;
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_Sat short _Fract sf_sat;
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_Sat _Fract f_sat;
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_Sat unsigned short _Accum usa_sat;
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_Sat unsigned _Accum ua_sat;
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_Sat unsigned short _Fract usf_sat;
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_Sat unsigned _Fract uf_sat;
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int i;
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unsigned u;
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// CHECK-LABEL: @sleft_sasai(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* @sa, align 2
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
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// CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
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// CHECK-NEXT: [[TMP3:%.*]] = shl i16 [[TMP0]], [[TMP2]]
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// CHECK-NEXT: store i16 [[TMP3]], i16* @sa, align 2
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// CHECK-NEXT: ret void
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//
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void sleft_sasai() {
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sa = sa << i;
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}
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// CHECK-LABEL: @sleft_aai(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
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// CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP0]], [[TMP1]]
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// CHECK-NEXT: store i32 [[TMP2]], i32* @a, align 4
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// CHECK-NEXT: ret void
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//
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void sleft_aai() {
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a = a << i;
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}
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// CHECK-LABEL: @sleft_lalai(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* @la, align 8
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
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// CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
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// CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP0]], [[TMP2]]
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// CHECK-NEXT: store i64 [[TMP3]], i64* @la, align 8
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// CHECK-NEXT: ret void
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//
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void sleft_lalai() {
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la = la << i;
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}
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// CHECK-LABEL: @sleft_sfsfi(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* @sf, align 1
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
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// CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
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// CHECK-NEXT: [[TMP3:%.*]] = shl i8 [[TMP0]], [[TMP2]]
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// CHECK-NEXT: store i8 [[TMP3]], i8* @sf, align 1
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// CHECK-NEXT: ret void
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//
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void sleft_sfsfi() {
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sf = sf << i;
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}
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// CHECK-LABEL: @sleft_ffi(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* @f, align 2
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
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// CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
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// CHECK-NEXT: [[TMP3:%.*]] = shl i16 [[TMP0]], [[TMP2]]
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// CHECK-NEXT: store i16 [[TMP3]], i16* @f, align 2
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// CHECK-NEXT: ret void
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//
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void sleft_ffi() {
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f = f << i;
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}
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// CHECK-LABEL: @sleft_lflfi(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @lf, align 4
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
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// CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP0]], [[TMP1]]
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// CHECK-NEXT: store i32 [[TMP2]], i32* @lf, align 4
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// CHECK-NEXT: ret void
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//
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void sleft_lflfi() {
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lf = lf << i;
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}
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// CHECK-LABEL: @sleft_aau(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @u, align 4
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// CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP0]], [[TMP1]]
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// CHECK-NEXT: store i32 [[TMP2]], i32* @a, align 4
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// CHECK-NEXT: ret void
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//
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void sleft_aau() {
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a = a << u;
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}
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// CHECK-LABEL: @sleft_ffu(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* @f, align 2
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @u, align 4
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// CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
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// CHECK-NEXT: [[TMP3:%.*]] = shl i16 [[TMP0]], [[TMP2]]
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// CHECK-NEXT: store i16 [[TMP3]], i16* @f, align 2
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// CHECK-NEXT: ret void
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//
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void sleft_ffu() {
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f = f << u;
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}
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// CHECK-LABEL: @uleft_usausai(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* @usa, align 2
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
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// CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
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// CHECK-NEXT: [[TMP3:%.*]] = shl i16 [[TMP0]], [[TMP2]]
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// CHECK-NEXT: store i16 [[TMP3]], i16* @usa, align 2
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// CHECK-NEXT: ret void
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//
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void uleft_usausai() {
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usa = usa << i;
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}
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// CHECK-LABEL: @uleft_uauai(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @ua, align 4
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
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// CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP0]], [[TMP1]]
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// CHECK-NEXT: store i32 [[TMP2]], i32* @ua, align 4
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// CHECK-NEXT: ret void
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//
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void uleft_uauai() {
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ua = ua << i;
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}
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// CHECK-LABEL: @uleft_ulaulai(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* @ula, align 8
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
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// CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
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// CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP0]], [[TMP2]]
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// CHECK-NEXT: store i64 [[TMP3]], i64* @ula, align 8
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// CHECK-NEXT: ret void
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//
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void uleft_ulaulai() {
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ula = ula << i;
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}
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// CHECK-LABEL: @uleft_usfusfi(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* @usf, align 1
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
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// CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
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// CHECK-NEXT: [[TMP3:%.*]] = shl i8 [[TMP0]], [[TMP2]]
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// CHECK-NEXT: store i8 [[TMP3]], i8* @usf, align 1
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// CHECK-NEXT: ret void
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//
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void uleft_usfusfi() {
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usf = usf << i;
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}
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// CHECK-LABEL: @uleft_ufufi(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* @uf, align 2
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
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// CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
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// CHECK-NEXT: [[TMP3:%.*]] = shl i16 [[TMP0]], [[TMP2]]
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// CHECK-NEXT: store i16 [[TMP3]], i16* @uf, align 2
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// CHECK-NEXT: ret void
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//
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void uleft_ufufi() {
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uf = uf << i;
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}
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// CHECK-LABEL: @uleft_ulfulfi(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @ulf, align 4
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
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// CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP0]], [[TMP1]]
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// CHECK-NEXT: store i32 [[TMP2]], i32* @ulf, align 4
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// CHECK-NEXT: ret void
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//
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void uleft_ulfulfi() {
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ulf = ulf << i;
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}
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// CHECK-LABEL: @uleft_uauau(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @ua, align 4
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @u, align 4
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// CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP0]], [[TMP1]]
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// CHECK-NEXT: store i32 [[TMP2]], i32* @ua, align 4
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// CHECK-NEXT: ret void
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//
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void uleft_uauau() {
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ua = ua << u;
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}
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// CHECK-LABEL: @uleft_ufufu(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* @uf, align 2
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @u, align 4
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// CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
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// CHECK-NEXT: [[TMP3:%.*]] = shl i16 [[TMP0]], [[TMP2]]
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// CHECK-NEXT: store i16 [[TMP3]], i16* @uf, align 2
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// CHECK-NEXT: ret void
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//
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void uleft_ufufu() {
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uf = uf << u;
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}
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// CHECK-LABEL: @sright_sasai(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* @sa, align 2
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
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// CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
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// CHECK-NEXT: [[TMP3:%.*]] = ashr i16 [[TMP0]], [[TMP2]]
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// CHECK-NEXT: store i16 [[TMP3]], i16* @sa, align 2
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// CHECK-NEXT: ret void
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//
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void sright_sasai() {
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sa = sa >> i;
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}
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// CHECK-LABEL: @sright_aai(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
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// CHECK-NEXT: [[TMP2:%.*]] = ashr i32 [[TMP0]], [[TMP1]]
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// CHECK-NEXT: store i32 [[TMP2]], i32* @a, align 4
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// CHECK-NEXT: ret void
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//
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void sright_aai() {
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a = a >> i;
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}
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// CHECK-LABEL: @sright_lalai(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* @la, align 8
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
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// CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
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// CHECK-NEXT: [[TMP3:%.*]] = ashr i64 [[TMP0]], [[TMP2]]
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// CHECK-NEXT: store i64 [[TMP3]], i64* @la, align 8
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// CHECK-NEXT: ret void
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//
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void sright_lalai() {
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la = la >> i;
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}
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// CHECK-LABEL: @sright_sfsfi(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* @sf, align 1
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
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// CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
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// CHECK-NEXT: [[TMP3:%.*]] = ashr i8 [[TMP0]], [[TMP2]]
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// CHECK-NEXT: store i8 [[TMP3]], i8* @sf, align 1
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// CHECK-NEXT: ret void
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//
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void sright_sfsfi() {
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sf = sf >> i;
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}
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// CHECK-LABEL: @sright_ffi(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* @f, align 2
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
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// CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
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// CHECK-NEXT: [[TMP3:%.*]] = ashr i16 [[TMP0]], [[TMP2]]
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// CHECK-NEXT: store i16 [[TMP3]], i16* @f, align 2
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// CHECK-NEXT: ret void
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//
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void sright_ffi() {
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f = f >> i;
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}
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// CHECK-LABEL: @sright_lflfi(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @lf, align 4
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
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// CHECK-NEXT: [[TMP2:%.*]] = ashr i32 [[TMP0]], [[TMP1]]
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// CHECK-NEXT: store i32 [[TMP2]], i32* @lf, align 4
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// CHECK-NEXT: ret void
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//
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void sright_lflfi() {
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lf = lf >> i;
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}
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|
|
// CHECK-LABEL: @sright_aau(
|
||
|
|
// CHECK-NEXT: entry:
|
||
|
|
// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4
|
||
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @u, align 4
|
||
|
|
// CHECK-NEXT: [[TMP2:%.*]] = ashr i32 [[TMP0]], [[TMP1]]
|
||
|
|
// CHECK-NEXT: store i32 [[TMP2]], i32* @a, align 4
|
||
|
|
// CHECK-NEXT: ret void
|
||
|
|
//
|
||
|
|
void sright_aau() {
|
||
|
|
a = a >> u;
|
||
|
|
}
|
||
|
|
|
||
|
|
// CHECK-LABEL: @sright_ffu(
|
||
|
|
// CHECK-NEXT: entry:
|
||
|
|
// CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* @f, align 2
|
||
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @u, align 4
|
||
|
|
// CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
|
||
|
|
// CHECK-NEXT: [[TMP3:%.*]] = ashr i16 [[TMP0]], [[TMP2]]
|
||
|
|
// CHECK-NEXT: store i16 [[TMP3]], i16* @f, align 2
|
||
|
|
// CHECK-NEXT: ret void
|
||
|
|
//
|
||
|
|
void sright_ffu() {
|
||
|
|
f = f >> u;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
// CHECK-LABEL: @uright_usausai(
|
||
|
|
// CHECK-NEXT: entry:
|
||
|
|
// CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* @usa, align 2
|
||
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
|
||
|
|
// CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
|
||
|
|
// CHECK-NEXT: [[TMP3:%.*]] = lshr i16 [[TMP0]], [[TMP2]]
|
||
|
|
// CHECK-NEXT: store i16 [[TMP3]], i16* @usa, align 2
|
||
|
|
// CHECK-NEXT: ret void
|
||
|
|
//
|
||
|
|
void uright_usausai() {
|
||
|
|
usa = usa >> i;
|
||
|
|
}
|
||
|
|
|
||
|
|
// CHECK-LABEL: @uright_uauai(
|
||
|
|
// CHECK-NEXT: entry:
|
||
|
|
// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @ua, align 4
|
||
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
|
||
|
|
// CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP0]], [[TMP1]]
|
||
|
|
// CHECK-NEXT: store i32 [[TMP2]], i32* @ua, align 4
|
||
|
|
// CHECK-NEXT: ret void
|
||
|
|
//
|
||
|
|
void uright_uauai() {
|
||
|
|
ua = ua >> i;
|
||
|
|
}
|
||
|
|
|
||
|
|
// CHECK-LABEL: @uright_ulaulai(
|
||
|
|
// CHECK-NEXT: entry:
|
||
|
|
// CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* @ula, align 8
|
||
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
|
||
|
|
// CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
|
||
|
|
// CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP0]], [[TMP2]]
|
||
|
|
// CHECK-NEXT: store i64 [[TMP3]], i64* @ula, align 8
|
||
|
|
// CHECK-NEXT: ret void
|
||
|
|
//
|
||
|
|
void uright_ulaulai() {
|
||
|
|
ula = ula >> i;
|
||
|
|
}
|
||
|
|
|
||
|
|
// CHECK-LABEL: @uright_usfusfi(
|
||
|
|
// CHECK-NEXT: entry:
|
||
|
|
// CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* @usf, align 1
|
||
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
|
||
|
|
// CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
|
||
|
|
// CHECK-NEXT: [[TMP3:%.*]] = lshr i8 [[TMP0]], [[TMP2]]
|
||
|
|
// CHECK-NEXT: store i8 [[TMP3]], i8* @usf, align 1
|
||
|
|
// CHECK-NEXT: ret void
|
||
|
|
//
|
||
|
|
void uright_usfusfi() {
|
||
|
|
usf = usf >> i;
|
||
|
|
}
|
||
|
|
|
||
|
|
// CHECK-LABEL: @uright_ufufi(
|
||
|
|
// CHECK-NEXT: entry:
|
||
|
|
// CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* @uf, align 2
|
||
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
|
||
|
|
// CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
|
||
|
|
// CHECK-NEXT: [[TMP3:%.*]] = lshr i16 [[TMP0]], [[TMP2]]
|
||
|
|
// CHECK-NEXT: store i16 [[TMP3]], i16* @uf, align 2
|
||
|
|
// CHECK-NEXT: ret void
|
||
|
|
//
|
||
|
|
void uright_ufufi() {
|
||
|
|
uf = uf >> i;
|
||
|
|
}
|
||
|
|
|
||
|
|
// CHECK-LABEL: @uright_ulfulfi(
|
||
|
|
// CHECK-NEXT: entry:
|
||
|
|
// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @ulf, align 4
|
||
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
|
||
|
|
// CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP0]], [[TMP1]]
|
||
|
|
// CHECK-NEXT: store i32 [[TMP2]], i32* @ulf, align 4
|
||
|
|
// CHECK-NEXT: ret void
|
||
|
|
//
|
||
|
|
void uright_ulfulfi() {
|
||
|
|
ulf = ulf >> i;
|
||
|
|
}
|
||
|
|
|
||
|
|
// CHECK-LABEL: @uright_uauau(
|
||
|
|
// CHECK-NEXT: entry:
|
||
|
|
// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @ua, align 4
|
||
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @u, align 4
|
||
|
|
// CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP0]], [[TMP1]]
|
||
|
|
// CHECK-NEXT: store i32 [[TMP2]], i32* @ua, align 4
|
||
|
|
// CHECK-NEXT: ret void
|
||
|
|
//
|
||
|
|
void uright_uauau() {
|
||
|
|
ua = ua >> u;
|
||
|
|
}
|
||
|
|
|
||
|
|
// CHECK-LABEL: @uright_ufufu(
|
||
|
|
// CHECK-NEXT: entry:
|
||
|
|
// CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* @uf, align 2
|
||
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @u, align 4
|
||
|
|
// CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
|
||
|
|
// CHECK-NEXT: [[TMP3:%.*]] = lshr i16 [[TMP0]], [[TMP2]]
|
||
|
|
// CHECK-NEXT: store i16 [[TMP3]], i16* @uf, align 2
|
||
|
|
// CHECK-NEXT: ret void
|
||
|
|
//
|
||
|
|
void uright_ufufu() {
|
||
|
|
uf = uf >> u;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
// CHECK-LABEL: @satleft_sassasi(
|
||
|
|
// CHECK-NEXT: entry:
|
||
|
|
// CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* @sa_sat, align 2
|
||
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
|
||
|
|
// CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
|
||
|
|
// CHECK-NEXT: [[TMP3:%.*]] = call i16 @llvm.sshl.sat.i16(i16 [[TMP0]], i16 [[TMP2]])
|
||
|
|
// CHECK-NEXT: store i16 [[TMP3]], i16* @sa_sat, align 2
|
||
|
|
// CHECK-NEXT: ret void
|
||
|
|
//
|
||
|
|
void satleft_sassasi() {
|
||
|
|
sa_sat = sa_sat << i;
|
||
|
|
}
|
||
|
|
|
||
|
|
// CHECK-LABEL: @satleft_asasi(
|
||
|
|
// CHECK-NEXT: entry:
|
||
|
|
// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @a_sat, align 4
|
||
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
|
||
|
|
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.sshl.sat.i32(i32 [[TMP0]], i32 [[TMP1]])
|
||
|
|
// CHECK-NEXT: store i32 [[TMP2]], i32* @a_sat, align 4
|
||
|
|
// CHECK-NEXT: ret void
|
||
|
|
//
|
||
|
|
void satleft_asasi() {
|
||
|
|
a_sat = a_sat << i;
|
||
|
|
}
|
||
|
|
|
||
|
|
// CHECK-LABEL: @satleft_sfssfsi(
|
||
|
|
// CHECK-NEXT: entry:
|
||
|
|
// CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* @sf_sat, align 1
|
||
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
|
||
|
|
// CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
|
||
|
|
// CHECK-NEXT: [[TMP3:%.*]] = call i8 @llvm.sshl.sat.i8(i8 [[TMP0]], i8 [[TMP2]])
|
||
|
|
// CHECK-NEXT: store i8 [[TMP3]], i8* @sf_sat, align 1
|
||
|
|
// CHECK-NEXT: ret void
|
||
|
|
//
|
||
|
|
void satleft_sfssfsi() {
|
||
|
|
sf_sat = sf_sat << i;
|
||
|
|
}
|
||
|
|
|
||
|
|
// CHECK-LABEL: @satleft_fsfsi(
|
||
|
|
// CHECK-NEXT: entry:
|
||
|
|
// CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* @f_sat, align 2
|
||
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
|
||
|
|
// CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
|
||
|
|
// CHECK-NEXT: [[TMP3:%.*]] = call i16 @llvm.sshl.sat.i16(i16 [[TMP0]], i16 [[TMP2]])
|
||
|
|
// CHECK-NEXT: store i16 [[TMP3]], i16* @f_sat, align 2
|
||
|
|
// CHECK-NEXT: ret void
|
||
|
|
//
|
||
|
|
void satleft_fsfsi() {
|
||
|
|
f_sat = f_sat << i;
|
||
|
|
}
|
||
|
|
|
||
|
|
// SIGNED-LABEL: @satleft_usasusasi(
|
||
|
|
// SIGNED-NEXT: entry:
|
||
|
|
// SIGNED-NEXT: [[TMP0:%.*]] = load i16, i16* @usa_sat, align 2
|
||
|
|
// SIGNED-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
|
||
|
|
// SIGNED-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
|
||
|
|
// SIGNED-NEXT: [[TMP3:%.*]] = call i16 @llvm.ushl.sat.i16(i16 [[TMP0]], i16 [[TMP2]])
|
||
|
|
// SIGNED-NEXT: store i16 [[TMP3]], i16* @usa_sat, align 2
|
||
|
|
// SIGNED-NEXT: ret void
|
||
|
|
//
|
||
|
|
// UNSIGNED-LABEL: @satleft_usasusasi(
|
||
|
|
// UNSIGNED-NEXT: entry:
|
||
|
|
// UNSIGNED-NEXT: [[TMP0:%.*]] = load i16, i16* @usa_sat, align 2
|
||
|
|
// UNSIGNED-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
|
||
|
|
// UNSIGNED-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
|
||
|
|
// UNSIGNED-NEXT: [[TMP3:%.*]] = call i16 @llvm.sshl.sat.i16(i16 [[TMP0]], i16 [[TMP2]])
|
||
|
|
// UNSIGNED-NEXT: store i16 [[TMP3]], i16* @usa_sat, align 2
|
||
|
|
// UNSIGNED-NEXT: ret void
|
||
|
|
//
|
||
|
|
void satleft_usasusasi() {
|
||
|
|
usa_sat = usa_sat << i;
|
||
|
|
}
|
||
|
|
|
||
|
|
// SIGNED-LABEL: @satleft_uasuasi(
|
||
|
|
// SIGNED-NEXT: entry:
|
||
|
|
// SIGNED-NEXT: [[TMP0:%.*]] = load i32, i32* @ua_sat, align 4
|
||
|
|
// SIGNED-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
|
||
|
|
// SIGNED-NEXT: [[TMP2:%.*]] = call i32 @llvm.ushl.sat.i32(i32 [[TMP0]], i32 [[TMP1]])
|
||
|
|
// SIGNED-NEXT: store i32 [[TMP2]], i32* @ua_sat, align 4
|
||
|
|
// SIGNED-NEXT: ret void
|
||
|
|
//
|
||
|
|
// UNSIGNED-LABEL: @satleft_uasuasi(
|
||
|
|
// UNSIGNED-NEXT: entry:
|
||
|
|
// UNSIGNED-NEXT: [[TMP0:%.*]] = load i32, i32* @ua_sat, align 4
|
||
|
|
// UNSIGNED-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
|
||
|
|
// UNSIGNED-NEXT: [[TMP2:%.*]] = call i32 @llvm.sshl.sat.i32(i32 [[TMP0]], i32 [[TMP1]])
|
||
|
|
// UNSIGNED-NEXT: store i32 [[TMP2]], i32* @ua_sat, align 4
|
||
|
|
// UNSIGNED-NEXT: ret void
|
||
|
|
//
|
||
|
|
void satleft_uasuasi() {
|
||
|
|
ua_sat = ua_sat << i;
|
||
|
|
}
|
||
|
|
|
||
|
|
// SIGNED-LABEL: @satleft_usfsusfsi(
|
||
|
|
// SIGNED-NEXT: entry:
|
||
|
|
// SIGNED-NEXT: [[TMP0:%.*]] = load i8, i8* @usf_sat, align 1
|
||
|
|
// SIGNED-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
|
||
|
|
// SIGNED-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
|
||
|
|
// SIGNED-NEXT: [[TMP3:%.*]] = call i8 @llvm.ushl.sat.i8(i8 [[TMP0]], i8 [[TMP2]])
|
||
|
|
// SIGNED-NEXT: store i8 [[TMP3]], i8* @usf_sat, align 1
|
||
|
|
// SIGNED-NEXT: ret void
|
||
|
|
//
|
||
|
|
// UNSIGNED-LABEL: @satleft_usfsusfsi(
|
||
|
|
// UNSIGNED-NEXT: entry:
|
||
|
|
// UNSIGNED-NEXT: [[TMP0:%.*]] = load i8, i8* @usf_sat, align 1
|
||
|
|
// UNSIGNED-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
|
||
|
|
// UNSIGNED-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
|
||
|
|
// UNSIGNED-NEXT: [[TMP3:%.*]] = call i8 @llvm.sshl.sat.i8(i8 [[TMP0]], i8 [[TMP2]])
|
||
|
|
// UNSIGNED-NEXT: store i8 [[TMP3]], i8* @usf_sat, align 1
|
||
|
|
// UNSIGNED-NEXT: ret void
|
||
|
|
//
|
||
|
|
void satleft_usfsusfsi() {
|
||
|
|
usf_sat = usf_sat << i;
|
||
|
|
}
|
||
|
|
|
||
|
|
// SIGNED-LABEL: @satleft_ufsufsi(
|
||
|
|
// SIGNED-NEXT: entry:
|
||
|
|
// SIGNED-NEXT: [[TMP0:%.*]] = load i16, i16* @uf_sat, align 2
|
||
|
|
// SIGNED-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
|
||
|
|
// SIGNED-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
|
||
|
|
// SIGNED-NEXT: [[TMP3:%.*]] = call i16 @llvm.ushl.sat.i16(i16 [[TMP0]], i16 [[TMP2]])
|
||
|
|
// SIGNED-NEXT: store i16 [[TMP3]], i16* @uf_sat, align 2
|
||
|
|
// SIGNED-NEXT: ret void
|
||
|
|
//
|
||
|
|
// UNSIGNED-LABEL: @satleft_ufsufsi(
|
||
|
|
// UNSIGNED-NEXT: entry:
|
||
|
|
// UNSIGNED-NEXT: [[TMP0:%.*]] = load i16, i16* @uf_sat, align 2
|
||
|
|
// UNSIGNED-NEXT: [[TMP1:%.*]] = load i32, i32* @i, align 4
|
||
|
|
// UNSIGNED-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
|
||
|
|
// UNSIGNED-NEXT: [[TMP3:%.*]] = call i16 @llvm.sshl.sat.i16(i16 [[TMP0]], i16 [[TMP2]])
|
||
|
|
// UNSIGNED-NEXT: store i16 [[TMP3]], i16* @uf_sat, align 2
|
||
|
|
// UNSIGNED-NEXT: ret void
|
||
|
|
//
|
||
|
|
void satleft_ufsufsi() {
|
||
|
|
uf_sat = uf_sat << i;
|
||
|
|
}
|