107 lines
4.6 KiB
ArmAsm
107 lines
4.6 KiB
ArmAsm
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-stats -dispatch-stats=false < %s | FileCheck %s -check-prefix=ALL
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# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-stats < %s | FileCheck %s -check-prefixes=ALL,FULL
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# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-stats -dispatch-stats < %s | FileCheck %s -check-prefixes=ALL,FULL
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# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -dispatch-stats -all-stats < %s | FileCheck %s -check-prefixes=ALL,FULL
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# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -dispatch-stats=false -all-stats < %s | FileCheck %s -check-prefixes=ALL,FULL
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add %eax, %eax
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# ALL: Iterations: 100
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# ALL-NEXT: Instructions: 100
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# ALL-NEXT: Total Cycles: 103
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# ALL-NEXT: Total uOps: 100
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# ALL: Dispatch Width: 2
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# ALL-NEXT: uOps Per Cycle: 0.97
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# ALL-NEXT: IPC: 0.97
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# ALL-NEXT: Block RThroughput: 0.5
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# ALL: Instruction Info:
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# ALL-NEXT: [1]: #uOps
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# ALL-NEXT: [2]: Latency
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# ALL-NEXT: [3]: RThroughput
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# ALL-NEXT: [4]: MayLoad
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# ALL-NEXT: [5]: MayStore
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# ALL-NEXT: [6]: HasSideEffects (U)
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# ALL: [1] [2] [3] [4] [5] [6] Instructions:
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# ALL-NEXT: 1 1 0.50 addl %eax, %eax
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# FULL: Dynamic Dispatch Stall Cycles:
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# FULL-NEXT: RAT - Register unavailable: 0
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# FULL-NEXT: RCU - Retire tokens unavailable: 0
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# FULL-NEXT: SCHEDQ - Scheduler full: 61 (59.2%)
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# FULL-NEXT: LQ - Load queue full: 0
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# FULL-NEXT: SQ - Store queue full: 0
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# FULL-NEXT: GROUP - Static restrictions on the dispatch group: 0
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# FULL: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
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# FULL-NEXT: [# dispatched], [# cycles]
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# FULL-NEXT: 0, 22 (21.4%)
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# FULL-NEXT: 1, 62 (60.2%)
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# FULL-NEXT: 2, 19 (18.4%)
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# ALL: Schedulers - number of cycles where we saw N micro opcodes issued:
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# ALL-NEXT: [# issued], [# cycles]
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# ALL-NEXT: 0, 3 (2.9%)
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# ALL-NEXT: 1, 100 (97.1%)
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# ALL: Scheduler's queue usage:
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# ALL-NEXT: [1] Resource name.
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# ALL-NEXT: [2] Average number of used buffer entries.
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# ALL-NEXT: [3] Maximum number of used buffer entries.
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# ALL-NEXT: [4] Total number of buffer entries.
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# ALL: [1] [2] [3] [4]
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# ALL-NEXT: JALU01 15 20 20
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# ALL-NEXT: JFPU01 0 0 18
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# ALL-NEXT: JLSAGU 0 0 12
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# ALL: Retire Control Unit - number of cycles where we saw N instructions retired:
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# ALL-NEXT: [# retired], [# cycles]
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# ALL-NEXT: 0, 3 (2.9%)
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# ALL-NEXT: 1, 100 (97.1%)
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# ALL: Total ROB Entries: 64
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# ALL-NEXT: Max Used ROB Entries: 22 ( 34.4% )
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# ALL-NEXT: Average Used ROB Entries per cy: 17 ( 26.6% )
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# ALL: Register File statistics:
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# ALL-NEXT: Total number of mappings created: 200
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# ALL-NEXT: Max number of mappings used: 44
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# ALL: * Register File #1 -- JFpuPRF:
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# ALL-NEXT: Number of physical registers: 72
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# ALL-NEXT: Total number of mappings created: 0
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# ALL-NEXT: Max number of mappings used: 0
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# ALL: * Register File #2 -- JIntegerPRF:
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# ALL-NEXT: Number of physical registers: 64
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# ALL-NEXT: Total number of mappings created: 200
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# ALL-NEXT: Max number of mappings used: 44
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# ALL: Resources:
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# ALL-NEXT: [0] - JALU0
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# ALL-NEXT: [1] - JALU1
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# ALL-NEXT: [2] - JDiv
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# ALL-NEXT: [3] - JFPA
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# ALL-NEXT: [4] - JFPM
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# ALL-NEXT: [5] - JFPU0
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# ALL-NEXT: [6] - JFPU1
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# ALL-NEXT: [7] - JLAGU
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# ALL-NEXT: [8] - JMul
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# ALL-NEXT: [9] - JSAGU
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# ALL-NEXT: [10] - JSTC
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# ALL-NEXT: [11] - JVALU0
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# ALL-NEXT: [12] - JVALU1
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# ALL-NEXT: [13] - JVIMUL
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# ALL: Resource pressure per iteration:
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# ALL-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
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# ALL-NEXT: 0.50 0.50 - - - - - - - - - - - -
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# ALL: Resource pressure by instruction:
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# ALL-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions:
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# ALL-NEXT: 0.50 0.50 - - - - - - - - - - - - addl %eax, %eax
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