46 lines
2.0 KiB
ArmAsm
46 lines
2.0 KiB
ArmAsm
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -lqueue=2 -iterations=2 -resource-pressure=false -timeline -timeline-max-cycles=104 < %s | FileCheck %s
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int3
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stmxcsr (%rsp)
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# CHECK: Iterations: 2
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# CHECK-NEXT: Instructions: 4
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# CHECK-NEXT: Total Cycles: 205
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# CHECK-NEXT: Total uOps: 4
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# CHECK: Dispatch Width: 2
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# CHECK-NEXT: uOps Per Cycle: 0.02
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# CHECK-NEXT: IPC: 0.02
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# CHECK-NEXT: Block RThroughput: 1.0
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 1 100 0.50 * * U int3
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# CHECK-NEXT: 1 1 1.00 * U stmxcsr (%rsp)
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# CHECK: Timeline view:
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# CHECK-NEXT: 0123456789 0123456789 0123456789 0123456789 0123456789
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# CHECK-NEXT: Index 0123456789 0123456789 0123456789 0123456789 0123456789 0123
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# CHECK: [0,0] DeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeER. int3
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# CHECK-NEXT: [0,1] D====================================================================================================eER stmxcsr (%rsp)
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# CHECK: Average Wait times (based on the timeline view):
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# CHECK-NEXT: [0]: Executions
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# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
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# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
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# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
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# CHECK: [0] [1] [2] [3]
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# CHECK-NEXT: 0. 2 51.0 0.5 0.0 int3
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# CHECK-NEXT: 1. 2 151.0 0.0 0.0 stmxcsr (%rsp)
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# CHECK-NEXT: 2 101.0 0.3 0.0 <total>
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