154 lines
7.1 KiB
ArmAsm
154 lines
7.1 KiB
ArmAsm
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m3 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M3
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# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M4
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# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m5 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M5
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ldr s0, 1f
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ldr q0, 1f
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ldur d0, [sp, #2]
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ldur q0, [sp, #16]
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ldr b0, [sp], #1
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ldr q0, [sp], #16
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ldr h0, [sp, #2]!
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ldr q0, [sp, #16]!
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ldr s0, [sp, #4]
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ldr q0, [sp, #16]
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ldr d0, [sp, x0, lsl #3]
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ldr q0, [sp, x0, lsl #4]
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ldr b0, [sp, x0]
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ldr q0, [sp, x0]
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ldr h0, [sp, w0, sxtw #1]
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ldr q0, [sp, w0, uxtw #4]
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ldr s0, [sp, w0, sxtw]
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ldr q0, [sp, w0, uxtw]
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ldp d0, d1, [sp], #16
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ldp q0, q1, [sp], #32
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ldp s0, s1, [sp, #8]!
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ldp q0, q1, [sp, #32]!
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ldp d0, d1, [sp, #16]
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ldp q0, q1, [sp, #32]
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1:
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# ALL: Iterations: 100
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# ALL-NEXT: Instructions: 2400
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# M3-NEXT: Total Cycles: 4708
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# M3-NEXT: Total uOps: 3200
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# M4-NEXT: Total Cycles: 4708
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# M4-NEXT: Total uOps: 3200
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# M5-NEXT: Total Cycles: 5509
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# M5-NEXT: Total uOps: 3300
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# ALL: Dispatch Width: 6
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# M3-NEXT: uOps Per Cycle: 0.68
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# M3-NEXT: IPC: 0.51
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# M3-NEXT: Block RThroughput: 13.5
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# M4-NEXT: uOps Per Cycle: 0.68
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# M4-NEXT: IPC: 0.51
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# M4-NEXT: Block RThroughput: 13.0
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# M5-NEXT: uOps Per Cycle: 0.60
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# M5-NEXT: IPC: 0.44
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# M5-NEXT: Block RThroughput: 13.5
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# ALL: Instruction Info:
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# ALL-NEXT: [1]: #uOps
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# ALL-NEXT: [2]: Latency
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# ALL-NEXT: [3]: RThroughput
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# ALL-NEXT: [4]: MayLoad
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# ALL-NEXT: [5]: MayStore
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# ALL-NEXT: [6]: HasSideEffects (U)
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# ALL: [1] [2] [3] [4] [5] [6] Instructions:
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# M3-NEXT: 1 5 0.50 * ldr s0, {{\.?}}Ltmp0
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# M3-NEXT: 1 5 0.50 * ldr q0, {{\.?}}Ltmp0
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# M3-NEXT: 1 5 0.50 * ldur d0, [sp, #2]
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# M3-NEXT: 1 5 0.50 * ldur q0, [sp, #16]
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# M3-NEXT: 1 5 0.50 * ldr b0, [sp], #1
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# M3-NEXT: 1 5 0.50 * ldr q0, [sp], #16
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# M3-NEXT: 1 5 0.50 * ldr h0, [sp, #2]!
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# M3-NEXT: 1 5 0.50 * ldr q0, [sp, #16]!
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# M3-NEXT: 1 5 0.50 * ldr s0, [sp, #4]
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# M3-NEXT: 1 5 0.50 * ldr q0, [sp, #16]
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# M3-NEXT: 1 5 0.50 * ldr d0, [sp, x0, lsl #3]
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# M3-NEXT: 2 6 0.50 * ldr q0, [sp, x0, lsl #4]
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# M3-NEXT: 1 5 0.50 * ldr b0, [sp, x0]
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# M3-NEXT: 1 5 0.50 * ldr q0, [sp, x0]
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# M3-NEXT: 2 6 0.50 * ldr h0, [sp, w0, sxtw #1]
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# M3-NEXT: 2 6 0.50 * ldr q0, [sp, w0, uxtw #4]
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# M3-NEXT: 2 6 0.50 * ldr s0, [sp, w0, sxtw]
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# M3-NEXT: 1 5 0.50 * ldr q0, [sp, w0, uxtw]
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# M3-NEXT: 2 5 0.50 * ldp d0, d1, [sp], #16
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# M3-NEXT: 2 5 1.00 * ldp q0, q1, [sp], #32
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# M3-NEXT: 2 5 0.50 * ldp s0, s1, [sp, #8]!
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# M3-NEXT: 2 5 1.00 * ldp q0, q1, [sp, #32]!
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# M3-NEXT: 1 5 0.50 * ldp d0, d1, [sp, #16]
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# M3-NEXT: 1 5 1.00 * ldp q0, q1, [sp, #32]
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# M4-NEXT: 1 5 0.50 * ldr s0, {{\.?}}Ltmp0
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# M4-NEXT: 1 5 0.50 * ldr q0, {{\.?}}Ltmp0
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# M4-NEXT: 1 5 0.50 * ldur d0, [sp, #2]
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# M4-NEXT: 1 5 0.50 * ldur q0, [sp, #16]
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# M4-NEXT: 1 5 0.50 * ldr b0, [sp], #1
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# M4-NEXT: 1 5 0.50 * ldr q0, [sp], #16
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# M4-NEXT: 1 5 0.50 * ldr h0, [sp, #2]!
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# M4-NEXT: 1 5 0.50 * ldr q0, [sp, #16]!
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# M4-NEXT: 1 5 0.50 * ldr s0, [sp, #4]
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# M4-NEXT: 1 5 0.50 * ldr q0, [sp, #16]
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# M4-NEXT: 1 5 0.50 * ldr d0, [sp, x0, lsl #3]
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# M4-NEXT: 2 6 0.50 * ldr q0, [sp, x0, lsl #4]
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# M4-NEXT: 1 5 0.50 * ldr b0, [sp, x0]
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# M4-NEXT: 1 5 0.50 * ldr q0, [sp, x0]
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# M4-NEXT: 2 6 0.50 * ldr h0, [sp, w0, sxtw #1]
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# M4-NEXT: 2 6 0.50 * ldr q0, [sp, w0, uxtw #4]
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# M4-NEXT: 2 6 0.50 * ldr s0, [sp, w0, sxtw]
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# M4-NEXT: 2 6 0.50 * ldr q0, [sp, w0, uxtw]
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# M4-NEXT: 1 5 0.50 * ldp d0, d1, [sp], #16
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# M4-NEXT: 2 5 0.50 * ldp q0, q1, [sp], #32
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# M4-NEXT: 2 5 0.50 * ldp s0, s1, [sp, #8]!
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# M4-NEXT: 2 5 1.00 * ldp q0, q1, [sp, #32]!
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# M4-NEXT: 1 5 0.50 * ldp d0, d1, [sp, #16]
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# M4-NEXT: 1 5 1.00 * ldp q0, q1, [sp, #32]
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# M5-NEXT: 1 6 0.50 * ldr s0, {{\.?}}Ltmp0
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# M5-NEXT: 1 6 0.50 * ldr q0, {{\.?}}Ltmp0
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# M5-NEXT: 1 6 0.50 * ldur d0, [sp, #2]
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# M5-NEXT: 1 6 0.50 * ldur q0, [sp, #16]
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# M5-NEXT: 1 6 0.50 * ldr b0, [sp], #1
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# M5-NEXT: 1 6 0.50 * ldr q0, [sp], #16
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# M5-NEXT: 1 6 0.50 * ldr h0, [sp, #2]!
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# M5-NEXT: 1 6 0.50 * ldr q0, [sp, #16]!
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# M5-NEXT: 1 6 0.50 * ldr s0, [sp, #4]
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# M5-NEXT: 1 6 0.50 * ldr q0, [sp, #16]
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# M5-NEXT: 1 6 0.50 * ldr d0, [sp, x0, lsl #3]
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# M5-NEXT: 2 7 0.50 * ldr q0, [sp, x0, lsl #4]
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# M5-NEXT: 1 6 0.50 * ldr b0, [sp, x0]
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# M5-NEXT: 1 6 0.50 * ldr q0, [sp, x0]
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# M5-NEXT: 2 7 0.50 * ldr h0, [sp, w0, sxtw #1]
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# M5-NEXT: 2 7 0.50 * ldr q0, [sp, w0, uxtw #4]
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# M5-NEXT: 2 7 0.50 * ldr s0, [sp, w0, sxtw]
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# M5-NEXT: 2 7 0.50 * ldr q0, [sp, w0, uxtw]
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# M5-NEXT: 2 6 0.50 * ldp d0, d1, [sp], #16
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# M5-NEXT: 2 6 1.00 * ldp q0, q1, [sp], #32
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# M5-NEXT: 2 6 0.50 * ldp s0, s1, [sp, #8]!
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# M5-NEXT: 2 6 1.00 * ldp q0, q1, [sp, #32]!
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# M5-NEXT: 1 6 0.50 * ldp d0, d1, [sp, #16]
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# M5-NEXT: 1 6 1.00 * ldp q0, q1, [sp, #32]
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