67 lines
2.3 KiB
ArmAsm
67 lines
2.3 KiB
ArmAsm
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m3 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M3
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# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M4
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# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m5 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M5
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fmov d31, #1.00000000
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fdiv d30, d31, d30
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# Newton series for 1 / x.
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frecpe d1, d0
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frecps d2, d0, d1
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fmul d1, d1, d2
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frecps d2, d0, d1
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fmul d1, d1, d2
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frecps d0, d0, d1
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fmul d0, d1, d0
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# ALL: Iterations: 100
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# ALL-NEXT: Instructions: 900
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# M3-NEXT: Total Cycles: 2503
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# M4-NEXT: Total Cycles: 2403
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# M5-NEXT: Total Cycles: 2403
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# ALL-NEXT: Total uOps: 900
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# ALL: Dispatch Width: 6
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# M3-NEXT: uOps Per Cycle: 0.36
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# M3-NEXT: IPC: 0.36
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# M3-NEXT: Block RThroughput: 3.3
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# M4-NEXT: uOps Per Cycle: 0.37
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# M4-NEXT: IPC: 0.37
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# M4-NEXT: Block RThroughput: 2.3
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# M5-NEXT: uOps Per Cycle: 0.37
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# M5-NEXT: IPC: 0.37
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# M5-NEXT: Block RThroughput: 2.3
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# ALL: Instruction Info:
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# ALL-NEXT: [1]: #uOps
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# ALL-NEXT: [2]: Latency
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# ALL-NEXT: [3]: RThroughput
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# ALL-NEXT: [4]: MayLoad
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# ALL-NEXT: [5]: MayStore
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# ALL-NEXT: [6]: HasSideEffects (U)
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# ALL: [1] [2] [3] [4] [5] [6] Instructions:
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# ALL-NEXT: 1 1 0.33 fmov d31, #1.00000000
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# M3-NEXT: 1 12 3.25 fdiv d30, d31, d30
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# M3-NEXT: 1 4 0.50 frecpe d1, d0
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# M4-NEXT: 1 12 2.25 fdiv d30, d31, d30
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# M4-NEXT: 1 3 0.50 frecpe d1, d0
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# M5-NEXT: 1 12 2.25 fdiv d30, d31, d30
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# M5-NEXT: 1 3 0.50 frecpe d1, d0
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# ALL-NEXT: 1 4 0.33 frecps d2, d0, d1
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# ALL-NEXT: 1 3 0.33 fmul d1, d1, d2
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# ALL-NEXT: 1 4 0.33 frecps d2, d0, d1
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# ALL-NEXT: 1 3 0.33 fmul d1, d1, d2
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# ALL-NEXT: 1 4 0.33 frecps d0, d0, d1
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# ALL-NEXT: 1 3 0.33 fmul d0, d1, d0
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