164 lines
7.9 KiB
LLVM
164 lines
7.9 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -structurizecfg %s | FileCheck %s
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;
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; StructurizeCFG::orderNodes basically uses a reverse post-order (RPO) traversal of the region
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; list to get the order. The only problem with it is that sometimes backedges
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; for outer loops will be visited before backedges for inner loops. To solve this problem,
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; a loop depth based approach has been used to make sure all blocks in this loop has been visited
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; before moving on to outer loop.
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;
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; However, we found a problem for a SubRegion which is a loop itself:
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; _
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; | |
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; V |
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; --> BB1 --> BB2 --> BB3 -->
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;
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; In this case, BB2 is a SubRegion (loop), and thus its loopdepth is different than that of
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; BB1 and BB3. This fact will lead BB2 to be placed in the wrong order.
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;
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; In this work, we treat the SubRegion as a special case and use its exit block to determine
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; the loop and its depth to guard the sorting.
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define amdgpu_kernel void @loop_subregion_misordered(i32 addrspace(1)* %arg0) #0 {
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; CHECK-LABEL: @loop_subregion_misordered(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP:%.*]] = load volatile <2 x i32>, <2 x i32> addrspace(1)* undef, align 16
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; CHECK-NEXT: [[LOAD1:%.*]] = load volatile <2 x float>, <2 x float> addrspace(1)* undef
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; CHECK-NEXT: [[TID:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, i32 addrspace(1)* [[ARG0:%.*]], i32 [[TID]]
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; CHECK-NEXT: [[I_INITIAL:%.*]] = load volatile i32, i32 addrspace(1)* [[GEP]], align 4
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; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
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; CHECK: LOOP.HEADER:
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; CHECK-NEXT: [[I:%.*]] = phi i32 [ [[I_INITIAL]], [[ENTRY:%.*]] ], [ [[TMP4:%.*]], [[FLOW3:%.*]] ]
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; CHECK-NEXT: call void asm sideeffect "s_nop 0x100b
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; CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[I]] to i64
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; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* null, i64 [[TMP12]]
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; CHECK-NEXT: [[TMP14:%.*]] = load <4 x i32>, <4 x i32> addrspace(1)* [[TMP13]], align 16
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; CHECK-NEXT: [[TMP15:%.*]] = extractelement <4 x i32> [[TMP14]], i64 0
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; CHECK-NEXT: [[TMP16:%.*]] = and i32 [[TMP15]], 65535
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; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i32 [[TMP16]], 1
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; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[TMP17]], true
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; CHECK-NEXT: br i1 [[TMP0]], label [[BB62:%.*]], label [[FLOW:%.*]]
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; CHECK: Flow1:
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; CHECK-NEXT: [[TMP1:%.*]] = phi i32 [ [[INC_I:%.*]], [[INCREMENT_I:%.*]] ], [ undef, [[BB62]] ]
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; CHECK-NEXT: [[TMP2:%.*]] = phi i1 [ false, [[INCREMENT_I]] ], [ true, [[BB62]] ]
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; CHECK-NEXT: [[TMP3:%.*]] = phi i1 [ true, [[INCREMENT_I]] ], [ false, [[BB62]] ]
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; CHECK-NEXT: br label [[FLOW]]
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; CHECK: bb18:
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; CHECK-NEXT: [[TMP19:%.*]] = extractelement <2 x i32> [[TMP]], i64 0
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; CHECK-NEXT: [[TMP22:%.*]] = lshr i32 [[TMP19]], 16
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; CHECK-NEXT: [[TMP24:%.*]] = urem i32 [[TMP22]], 52
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; CHECK-NEXT: [[TMP25:%.*]] = mul nuw nsw i32 [[TMP24]], 52
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; CHECK-NEXT: br label [[INNER_LOOP:%.*]]
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; CHECK: Flow2:
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; CHECK-NEXT: [[TMP4]] = phi i32 [ [[TMP59:%.*]], [[INNER_LOOP_BREAK:%.*]] ], [ [[TMP8:%.*]], [[FLOW]] ]
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; CHECK-NEXT: [[TMP5:%.*]] = phi i1 [ true, [[INNER_LOOP_BREAK]] ], [ [[TMP10:%.*]], [[FLOW]] ]
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; CHECK-NEXT: br i1 [[TMP5]], label [[END_ELSE_BLOCK:%.*]], label [[FLOW3]]
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; CHECK: INNER_LOOP:
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; CHECK-NEXT: [[INNER_LOOP_J:%.*]] = phi i32 [ [[INNER_LOOP_J_INC:%.*]], [[INNER_LOOP]] ], [ [[TMP25]], [[BB18:%.*]] ]
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; CHECK-NEXT: call void asm sideeffect "
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; CHECK-NEXT: [[INNER_LOOP_J_INC]] = add nsw i32 [[INNER_LOOP_J]], 1
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; CHECK-NEXT: [[INNER_LOOP_CMP:%.*]] = icmp eq i32 [[INNER_LOOP_J]], 0
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; CHECK-NEXT: br i1 [[INNER_LOOP_CMP]], label [[INNER_LOOP_BREAK]], label [[INNER_LOOP]]
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; CHECK: INNER_LOOP_BREAK:
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; CHECK-NEXT: [[TMP59]] = extractelement <4 x i32> [[TMP14]], i64 2
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; CHECK-NEXT: call void asm sideeffect "s_nop 23 ", "~{memory}"() #0
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; CHECK-NEXT: br label [[FLOW2:%.*]]
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; CHECK: bb62:
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; CHECK-NEXT: [[LOAD13:%.*]] = icmp ult i32 [[TMP16]], 271
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; CHECK-NEXT: [[TMP6:%.*]] = xor i1 [[LOAD13]], true
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; CHECK-NEXT: br i1 [[TMP6]], label [[INCREMENT_I]], label [[FLOW1:%.*]]
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; CHECK: Flow3:
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; CHECK-NEXT: [[TMP7:%.*]] = phi i1 [ [[CMP_END_ELSE_BLOCK:%.*]], [[END_ELSE_BLOCK]] ], [ true, [[FLOW2]] ]
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; CHECK-NEXT: br i1 [[TMP7]], label [[FLOW4:%.*]], label [[LOOP_HEADER]]
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; CHECK: Flow4:
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; CHECK-NEXT: br i1 [[TMP9:%.*]], label [[BB64:%.*]], label [[RETURN:%.*]]
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; CHECK: bb64:
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; CHECK-NEXT: call void asm sideeffect "s_nop 42", "~{memory}"() #0
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; CHECK-NEXT: br label [[RETURN]]
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; CHECK: Flow:
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; CHECK-NEXT: [[TMP8]] = phi i32 [ [[TMP1]], [[FLOW1]] ], [ undef, [[LOOP_HEADER]] ]
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; CHECK-NEXT: [[TMP9]] = phi i1 [ [[TMP2]], [[FLOW1]] ], [ false, [[LOOP_HEADER]] ]
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; CHECK-NEXT: [[TMP10]] = phi i1 [ [[TMP3]], [[FLOW1]] ], [ false, [[LOOP_HEADER]] ]
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; CHECK-NEXT: [[TMP11:%.*]] = phi i1 [ false, [[FLOW1]] ], [ true, [[LOOP_HEADER]] ]
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; CHECK-NEXT: br i1 [[TMP11]], label [[BB18]], label [[FLOW2]]
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; CHECK: INCREMENT_I:
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; CHECK-NEXT: [[INC_I]] = add i32 [[I]], 1
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; CHECK-NEXT: call void asm sideeffect "s_nop 0x1336
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; CHECK-NEXT: br label [[FLOW1]]
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; CHECK: END_ELSE_BLOCK:
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; CHECK-NEXT: call void asm sideeffect "s_nop 0x1337
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; CHECK-NEXT: [[CMP_END_ELSE_BLOCK]] = icmp eq i32 [[TMP4]], -1
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; CHECK-NEXT: br label [[FLOW3]]
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; CHECK: RETURN:
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; CHECK-NEXT: call void asm sideeffect "s_nop 0x99
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; CHECK-NEXT: store volatile <2 x float> [[LOAD1]], <2 x float> addrspace(1)* undef, align 8
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; CHECK-NEXT: ret void
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;
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entry:
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%tmp = load volatile <2 x i32>, <2 x i32> addrspace(1)* undef, align 16
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%load1 = load volatile <2 x float>, <2 x float> addrspace(1)* undef
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg0, i32 %tid
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%i.initial = load volatile i32, i32 addrspace(1)* %gep, align 4
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br label %LOOP.HEADER
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LOOP.HEADER:
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%i = phi i32 [ %i.final, %END_ELSE_BLOCK ], [ %i.initial, %entry ]
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call void asm sideeffect "s_nop 0x100b ; loop $0 ", "r,~{memory}"(i32 %i) #0
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%tmp12 = zext i32 %i to i64
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%tmp13 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* null, i64 %tmp12
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%tmp14 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp13, align 16
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%tmp15 = extractelement <4 x i32> %tmp14, i64 0
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%tmp16 = and i32 %tmp15, 65535
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%tmp17 = icmp eq i32 %tmp16, 1
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br i1 %tmp17, label %bb18, label %bb62
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bb18:
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%tmp19 = extractelement <2 x i32> %tmp, i64 0
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%tmp22 = lshr i32 %tmp19, 16
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%tmp24 = urem i32 %tmp22, 52
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%tmp25 = mul nuw nsw i32 %tmp24, 52
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br label %INNER_LOOP
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INNER_LOOP:
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%inner.loop.j = phi i32 [ %tmp25, %bb18 ], [ %inner.loop.j.inc, %INNER_LOOP ]
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call void asm sideeffect "; inner loop body", ""() #0
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%inner.loop.j.inc = add nsw i32 %inner.loop.j, 1
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%inner.loop.cmp = icmp eq i32 %inner.loop.j, 0
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br i1 %inner.loop.cmp, label %INNER_LOOP_BREAK, label %INNER_LOOP
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INNER_LOOP_BREAK:
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%tmp59 = extractelement <4 x i32> %tmp14, i64 2
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call void asm sideeffect "s_nop 23 ", "~{memory}"() #0
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br label %END_ELSE_BLOCK
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bb62:
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%load13 = icmp ult i32 %tmp16, 271
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br i1 %load13, label %bb64, label %INCREMENT_I
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bb64:
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call void asm sideeffect "s_nop 42", "~{memory}"() #0
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br label %RETURN
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INCREMENT_I:
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%inc.i = add i32 %i, 1
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call void asm sideeffect "s_nop 0x1336 ; increment $0", "v,~{memory}"(i32 %inc.i) #0
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br label %END_ELSE_BLOCK
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END_ELSE_BLOCK:
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%i.final = phi i32 [ %tmp59, %INNER_LOOP_BREAK ], [ %inc.i, %INCREMENT_I ]
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call void asm sideeffect "s_nop 0x1337 ; end else block $0", "v,~{memory}"(i32 %i.final) #0
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%cmp.end.else.block = icmp eq i32 %i.final, -1
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br i1 %cmp.end.else.block, label %RETURN, label %LOOP.HEADER
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RETURN:
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call void asm sideeffect "s_nop 0x99 ; ClosureEval return", "~{memory}"() #0
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store volatile <2 x float> %load1, <2 x float> addrspace(1)* undef, align 8
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { convergent nounwind }
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attributes #1 = { convergent nounwind readnone }
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