40 lines
1.7 KiB
LLVM
40 lines
1.7 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -slp-vectorizer -instcombine -S | FileCheck %s
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; Regression test for a bug in the SLP vectorizer that was causing
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; these rotates to be incorrectly combined into a vector rotate.
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; The bug fix is at https://reviews.llvm.org/D85759. This test has
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; been pre-committed to demonstrate the regressed behavior and provide
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; a clear diff for the bug fix.
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target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
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target triple = "wasm32-unknown-unknown"
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define void @foo(<2 x i64> %x, <4 x i32> %y, i64* %out) #0 {
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; CHECK-LABEL: @foo(
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; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[Y:%.*]], <4 x i32> undef, <2 x i32> <i32 2, i32 3>
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; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
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; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[X:%.*]], <2 x i64> [[X]], <2 x i64> [[TMP2]])
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; CHECK-NEXT: [[TMP4:%.*]] = bitcast i64* [[OUT:%.*]] to <2 x i64>*
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; CHECK-NEXT: store <2 x i64> [[TMP3]], <2 x i64>* [[TMP4]], align 8
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; CHECK-NEXT: ret void
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;
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%a = extractelement <2 x i64> %x, i32 0
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%b = extractelement <4 x i32> %y, i32 2
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%conv6 = zext i32 %b to i64
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%c = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %conv6)
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store i64 %c, i64* %out
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%d = extractelement <2 x i64> %x, i32 1
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%e = extractelement <4 x i32> %y, i32 3
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%conv17 = zext i32 %e to i64
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%f = tail call i64 @llvm.fshl.i64(i64 %d, i64 %d, i64 %conv17)
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%arrayidx2 = getelementptr inbounds i64, i64* %out, i32 1
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store i64 %f, i64* %arrayidx2
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ret void
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}
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declare i64 @llvm.fshl.i64(i64, i64, i64)
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attributes #0 = {"target-cpu"="generic" "target-features"="+simd128"}
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