111 lines
4.8 KiB
LLVM
111 lines
4.8 KiB
LLVM
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; RUN: opt < %s -loop-vectorize -force-vector-width=4 -force-vector-interleave=2 -debug-only=vectorutils -disable-output -enable-interleaved-mem-accesses=true 2>&1 | FileCheck %s
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; REQUIRES: asserts
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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; PR40291
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; The loop does the following operation 3 times:
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; 1. Load x from memory;
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; 2. Store (x + 1) to this memory;
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; 3. if (x < 1), store 0 to this memory.
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; When scalar version stores 0 in all locations, the vector version should do
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; the same thing. However, with interleaving it does not honour the WAW dependency between
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; store 0 and store (x + 1) to the same memory.
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; For now, we identify such unsafe dependency and disable adding the
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; store into the interleaved group.
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; In this test case, because we disable adding store into i32* %storeaddr12 and
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; storeaddr22, we create interleaved groups with gaps and
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; disable that interleaved group. So, we are only left with valid interleaved
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; groups.
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; CHECK: LV: Analyzing interleaved accesses...
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; CHECK: LV: Creating an interleave group with: store i32 %tmp34, i32* %storeaddr32, align 4
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; CHECK-NEXT: LV: Inserted: store i32 %tmp24, i32* %storeaddr22, align 4
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; CHECK-NEXT: into the interleave group with store i32 %tmp34, i32* %storeaddr32, align 4
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; CHECK-NEXT: LV: Inserted: store i32 %tmp14, i32* %storeaddr12, align 4
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; CHECK-NEXT: into the interleave group with store i32 %tmp34, i32* %storeaddr32, align 4
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; CHECK: LV: Invalidated store group due to dependence between store i32 %tmp24, i32* %storeaddr22, align 4 and store i32 0, i32* %storeaddr22, align 4
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; CHECK-NEXT: LV: Creating an interleave group with: store i32 %tmp24, i32* %storeaddr22, align 4
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; CHECK-NEXT: LV: Inserted: store i32 %tmp14, i32* %storeaddr12, align 4
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; CHECK-NEXT: into the interleave group with store i32 %tmp24, i32* %storeaddr22, align 4
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; CHECK-NEXT: LV: Invalidated store group due to dependence between store i32 %tmp14, i32* %storeaddr12, align 4 and store i32 0, i32* %storeaddr12, align 4
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define void @test(i8* nonnull align 8 dereferenceable_or_null(24) %arg) {
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bb:
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%tmp = getelementptr inbounds i8, i8* %arg, i64 16
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%tmp1 = bitcast i8* %tmp to i8**
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%tmp2 = load i8*, i8** %tmp1, align 8
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%tmp3 = getelementptr inbounds i8, i8* %arg, i64 8
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%tmp4 = bitcast i8* %tmp3 to i8**
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%tmp5 = load i8*, i8** %tmp4, align 8
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%tmp6 = getelementptr inbounds i8, i8* %tmp5, i64 12
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%tmp7 = bitcast i8* %tmp6 to i32*
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%tmp8 = getelementptr inbounds i8, i8* %tmp2, i64 12
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br label %header
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header: ; preds = %latch, %bb
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%tmp10 = phi i64 [ %tmp41, %latch ], [ 3, %bb ]
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%tmp11 = add nsw i64 %tmp10, -1
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%storeaddr12 = getelementptr inbounds i32, i32* %tmp7, i64 %tmp11
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%tmp13 = load i32, i32* %storeaddr12, align 4
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%tmp14 = add i32 %tmp13, 1
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store i32 %tmp14, i32* %storeaddr12, align 4
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%tmp15 = icmp slt i32 %tmp13, 1
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%tmp16 = xor i1 %tmp15, true
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%tmp17 = zext i1 %tmp16 to i8
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%tmp18 = getelementptr inbounds i8, i8* %tmp8, i64 %tmp10
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store i8 %tmp17, i8* %tmp18, align 1
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br i1 %tmp15, label %bb19, label %bb20
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bb19: ; preds = %header
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store i32 0, i32* %storeaddr12, align 4
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br label %bb20
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bb20: ; preds = %bb19, %header
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%tmp21 = add nuw nsw i64 %tmp10, 1
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%storeaddr22 = getelementptr inbounds i32, i32* %tmp7, i64 %tmp10
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%tmp23 = load i32, i32* %storeaddr22, align 4
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%tmp24 = add i32 %tmp23, 1
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store i32 %tmp24, i32* %storeaddr22, align 4
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%tmp25 = icmp slt i32 %tmp23, 1
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%tmp26 = xor i1 %tmp25, true
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%tmp27 = zext i1 %tmp26 to i8
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%tmp28 = getelementptr inbounds i8, i8* %tmp8, i64 %tmp21
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store i8 %tmp27, i8* %tmp28, align 1
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br i1 %tmp25, label %bb29, label %bb30
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bb29: ; preds = %bb20
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store i32 0, i32* %storeaddr22, align 4
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br label %bb30
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bb30: ; preds = %bb29, %bb20
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%tmp31 = add nuw nsw i64 %tmp10, 2
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%storeaddr32 = getelementptr inbounds i32, i32* %tmp7, i64 %tmp21
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%tmp33 = load i32, i32* %storeaddr32, align 4
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%tmp34 = add i32 %tmp33, 1
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store i32 %tmp34, i32* %storeaddr32, align 4
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%tmp35 = icmp slt i32 %tmp33, 1
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%tmp36 = xor i1 %tmp35, true
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%tmp37 = zext i1 %tmp36 to i8
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%tmp38 = getelementptr inbounds i8, i8* %tmp8, i64 %tmp31
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store i8 %tmp37, i8* %tmp38, align 1
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br i1 %tmp35, label %bb39, label %latch
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bb39: ; preds = %bb30
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store i32 0, i32* %storeaddr32, align 4
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br label %latch
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latch: ; preds = %bb39, %bb30
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%tmp41 = add nuw nsw i64 %tmp10, 3
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%tmp42 = icmp ugt i64 %tmp31, 67
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br i1 %tmp42, label %exit, label %header
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exit: ; preds = %latch
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ret void
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}
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