96 lines
3.5 KiB
LLVM
96 lines
3.5 KiB
LLVM
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; RUN: opt -loop-vectorize -hexagon-autohvx=1 -force-vector-width=64 -prefer-predicate-over-epilogue=predicate-dont-vectorize -S %s | FileCheck %s
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target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
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target triple = "hexagon"
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; Test for PR45572.
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; Check that interleave groups and decisions based on them are correctly
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; invalidated with tail-folding on platforms where masked interleaved accesses
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; are disabled.
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; Make sure a vector body has been created, 64 element vectors are used and a block predicate has been computed.
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; Also make sure the loads are not widened.
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; CHECK-LABEL: @test1
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; CHECK: vector.body:
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; CHECK: icmp ule <64 x i32> %vec.ind
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; CHECK-NOT: load <{{.*}} x i32>
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define void @test1(i32* %arg, i32 %N) #0 {
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entry:
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%tmp = alloca i8
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br label %loop
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loop: ; preds = %bb2, %bb
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%iv = phi i32 [ %iv.next, %loop], [ 0, %entry ]
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%idx.mul = mul nuw nsw i32 %iv, 7
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%idx.start = add nuw nsw i32 %idx.mul, 1
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%tmp6 = getelementptr inbounds i32, i32* %arg, i32 %idx.start
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%tmp7 = load i32, i32* %tmp6, align 4
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%tmp8 = add nuw nsw i32 %idx.start, 1
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%tmp9 = getelementptr inbounds i32, i32* %arg, i32 %tmp8
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%tmp10 = load i32, i32* %tmp9, align 4
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%tmp11 = add nuw nsw i32 %idx.start, 2
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%tmp12 = getelementptr inbounds i32, i32* %arg, i32 %tmp11
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%tmp13 = load i32, i32* %tmp12, align 4
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%tmp14 = add nuw nsw i32 %idx.start, 3
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%tmp15 = getelementptr inbounds i32, i32* %arg, i32 %tmp14
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%tmp16 = load i32, i32* %tmp15, align 4
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%tmp18 = add nuw nsw i32 %idx.start, 4
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%tmp19 = getelementptr inbounds i32, i32* %arg, i32 %tmp18
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%tmp20 = load i32, i32* %tmp19, align 4
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%tmp21 = add nuw nsw i32 %idx.start, 5
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%tmp22 = getelementptr inbounds i32, i32* %arg, i32 %tmp21
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%tmp23 = load i32, i32* %tmp22, align 4
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%tmp25 = add nuw nsw i32 %idx.start, 6
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%tmp26 = getelementptr inbounds i32, i32* %arg, i32 %tmp25
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%tmp27 = load i32, i32* %tmp26, align 4
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store i8 0, i8* %tmp, align 1
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%iv.next= add nuw nsw i32 %iv, 1
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%exit.cond = icmp eq i32 %iv.next, %N
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br i1 %exit.cond, label %exit, label %loop
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exit: ; preds = %loop
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ret void
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}
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; The loop below only requires tail folding due to interleave groups with gaps.
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; Make sure the loads are not widened.
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; CHECK-LABEL: @test2
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; CHECK: vector.body:
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; CHECK-NOT: load <{{.*}} x i32>
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define void @test2(i32* %arg) #1 {
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entry:
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%tmp = alloca i8
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br label %loop
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loop: ; preds = %bb2, %bb
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%iv = phi i32 [ %iv.next, %loop], [ 0, %entry ]
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%idx.start = mul nuw nsw i32 %iv, 5
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%tmp6 = getelementptr inbounds i32, i32* %arg, i32 %idx.start
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%tmp7 = load i32, i32* %tmp6, align 4
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%tmp8 = add nuw nsw i32 %idx.start, 1
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%tmp9 = getelementptr inbounds i32, i32* %arg, i32 %tmp8
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%tmp10 = load i32, i32* %tmp9, align 4
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%tmp11 = add nuw nsw i32 %idx.start, 2
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%tmp12 = getelementptr inbounds i32, i32* %arg, i32 %tmp11
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%tmp13 = load i32, i32* %tmp12, align 4
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%tmp14 = add nuw nsw i32 %idx.start, 3
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%tmp15 = getelementptr inbounds i32, i32* %arg, i32 %tmp14
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%tmp16 = load i32, i32* %tmp15, align 4
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store i8 0, i8* %tmp, align 1
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%iv.next= add nuw nsw i32 %iv, 1
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%exit.cond = icmp eq i32 %iv.next, 128
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br i1 %exit.cond, label %exit, label %loop
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exit: ; preds = %loop
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ret void
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}
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attributes #0 = { "target-features"="+hvx,+hvx-length128b" }
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attributes #1 = { optsize "target-features"="+hvx,+hvx-length128b" }
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