112 lines
7.0 KiB
LLVM
112 lines
7.0 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -mtriple=x86_64-unknown-unknown -S | FileCheck %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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define i16 @test1(float %f) {
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; CHECK-LABEL: @test1(
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; CHECK-NEXT: [[TMP1:%.*]] = fadd float [[F:%.*]], -1.000000e+00
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; CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 5.000000e-01
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; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
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; CHECK-NEXT: [[TMP48:%.*]] = tail call <4 x float> @llvm.x86.sse.min.ss(<4 x float> [[TMP3]], <4 x float> <float 6.553500e+04, float poison, float poison, float poison>)
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; CHECK-NEXT: [[TMP59:%.*]] = tail call <4 x float> @llvm.x86.sse.max.ss(<4 x float> [[TMP48]], <4 x float> <float 0.000000e+00, float poison, float poison, float poison>)
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; CHECK-NEXT: [[TMP_UPGRD_1:%.*]] = tail call i32 @llvm.x86.sse.cvttss2si(<4 x float> [[TMP59]])
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; CHECK-NEXT: [[TMP69:%.*]] = trunc i32 [[TMP_UPGRD_1]] to i16
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; CHECK-NEXT: ret i16 [[TMP69]]
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;
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%tmp = insertelement <4 x float> undef, float %f, i32 0
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%tmp10 = insertelement <4 x float> %tmp, float 0.000000e+00, i32 1
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%tmp11 = insertelement <4 x float> %tmp10, float 0.000000e+00, i32 2
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%tmp12 = insertelement <4 x float> %tmp11, float 0.000000e+00, i32 3
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%tmp28 = tail call <4 x float> @llvm.x86.sse.sub.ss( <4 x float> %tmp12, <4 x float> < float 1.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00 > )
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%tmp37 = tail call <4 x float> @llvm.x86.sse.mul.ss( <4 x float> %tmp28, <4 x float> < float 5.000000e-01, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00 > )
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%tmp48 = tail call <4 x float> @llvm.x86.sse.min.ss( <4 x float> %tmp37, <4 x float> < float 6.553500e+04, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00 > )
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%tmp59 = tail call <4 x float> @llvm.x86.sse.max.ss( <4 x float> %tmp48, <4 x float> zeroinitializer )
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%tmp.upgrd.1 = tail call i32 @llvm.x86.sse.cvttss2si( <4 x float> %tmp59 )
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%tmp69 = trunc i32 %tmp.upgrd.1 to i16
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ret i16 %tmp69
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}
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define i64 @test3(float %f, double %d) {
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; CHECK-LABEL: @test3(
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; CHECK-NEXT: [[V03:%.*]] = insertelement <4 x float> poison, float [[F:%.*]], i32 0
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; CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.x86.sse.cvtss2si(<4 x float> [[V03]])
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; CHECK-NEXT: [[V13:%.*]] = insertelement <4 x float> poison, float [[F]], i32 0
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; CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.x86.sse.cvtss2si64(<4 x float> [[V13]])
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; CHECK-NEXT: [[V23:%.*]] = insertelement <4 x float> poison, float [[F]], i32 0
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; CHECK-NEXT: [[TMP2:%.*]] = tail call i32 @llvm.x86.sse.cvttss2si(<4 x float> [[V23]])
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; CHECK-NEXT: [[V33:%.*]] = insertelement <4 x float> poison, float [[F]], i32 0
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; CHECK-NEXT: [[TMP3:%.*]] = tail call i64 @llvm.x86.sse.cvttss2si64(<4 x float> [[V33]])
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; CHECK-NEXT: [[V41:%.*]] = insertelement <2 x double> poison, double [[D:%.*]], i32 0
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; CHECK-NEXT: [[TMP4:%.*]] = tail call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> [[V41]])
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; CHECK-NEXT: [[V51:%.*]] = insertelement <2 x double> poison, double [[D]], i32 0
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; CHECK-NEXT: [[TMP5:%.*]] = tail call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> [[V51]])
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; CHECK-NEXT: [[V61:%.*]] = insertelement <2 x double> poison, double [[D]], i32 0
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; CHECK-NEXT: [[TMP6:%.*]] = tail call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> [[V61]])
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; CHECK-NEXT: [[V71:%.*]] = insertelement <2 x double> poison, double [[D]], i32 0
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; CHECK-NEXT: [[TMP7:%.*]] = tail call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> [[V71]])
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; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP0]], [[TMP2]]
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; CHECK-NEXT: [[TMP9:%.*]] = add i32 [[TMP4]], [[TMP6]]
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; CHECK-NEXT: [[TMP10:%.*]] = add i32 [[TMP8]], [[TMP9]]
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; CHECK-NEXT: [[TMP11:%.*]] = sext i32 [[TMP10]] to i64
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; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[TMP1]], [[TMP3]]
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; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[TMP5]], [[TMP7]]
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; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[TMP12]], [[TMP13]]
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; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[TMP14]], [[TMP11]]
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; CHECK-NEXT: ret i64 [[TMP15]]
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;
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%v00 = insertelement <4 x float> undef, float %f, i32 0
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%v01 = insertelement <4 x float> %v00, float 0.000000e+00, i32 1
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%v02 = insertelement <4 x float> %v01, float 0.000000e+00, i32 2
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%v03 = insertelement <4 x float> %v02, float 0.000000e+00, i32 3
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%tmp0 = tail call i32 @llvm.x86.sse.cvtss2si(<4 x float> %v03)
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%v10 = insertelement <4 x float> undef, float %f, i32 0
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%v11 = insertelement <4 x float> %v10, float 0.000000e+00, i32 1
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%v12 = insertelement <4 x float> %v11, float 0.000000e+00, i32 2
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%v13 = insertelement <4 x float> %v12, float 0.000000e+00, i32 3
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%tmp1 = tail call i64 @llvm.x86.sse.cvtss2si64(<4 x float> %v13)
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%v20 = insertelement <4 x float> undef, float %f, i32 0
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%v21 = insertelement <4 x float> %v20, float 0.000000e+00, i32 1
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%v22 = insertelement <4 x float> %v21, float 0.000000e+00, i32 2
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%v23 = insertelement <4 x float> %v22, float 0.000000e+00, i32 3
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%tmp2 = tail call i32 @llvm.x86.sse.cvttss2si(<4 x float> %v23)
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%v30 = insertelement <4 x float> undef, float %f, i32 0
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%v31 = insertelement <4 x float> %v30, float 0.000000e+00, i32 1
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%v32 = insertelement <4 x float> %v31, float 0.000000e+00, i32 2
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%v33 = insertelement <4 x float> %v32, float 0.000000e+00, i32 3
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%tmp3 = tail call i64 @llvm.x86.sse.cvttss2si64(<4 x float> %v33)
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%v40 = insertelement <2 x double> undef, double %d, i32 0
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%v41 = insertelement <2 x double> %v40, double 0.000000e+00, i32 1
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%tmp4 = tail call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> %v41)
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%v50 = insertelement <2 x double> undef, double %d, i32 0
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%v51 = insertelement <2 x double> %v50, double 0.000000e+00, i32 1
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%tmp5 = tail call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %v51)
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%v60 = insertelement <2 x double> undef, double %d, i32 0
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%v61 = insertelement <2 x double> %v60, double 0.000000e+00, i32 1
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%tmp6 = tail call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> %v61)
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%v70 = insertelement <2 x double> undef, double %d, i32 0
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%v71 = insertelement <2 x double> %v70, double 0.000000e+00, i32 1
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%tmp7 = tail call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %v71)
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%tmp8 = add i32 %tmp0, %tmp2
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%tmp9 = add i32 %tmp4, %tmp6
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%tmp10 = add i32 %tmp8, %tmp9
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%tmp11 = sext i32 %tmp10 to i64
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%tmp12 = add i64 %tmp1, %tmp3
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%tmp13 = add i64 %tmp5, %tmp7
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%tmp14 = add i64 %tmp12, %tmp13
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%tmp15 = add i64 %tmp11, %tmp14
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ret i64 %tmp15
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}
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declare <4 x float> @llvm.x86.sse.sub.ss(<4 x float>, <4 x float>)
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declare <4 x float> @llvm.x86.sse.mul.ss(<4 x float>, <4 x float>)
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declare <4 x float> @llvm.x86.sse.min.ss(<4 x float>, <4 x float>)
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declare <4 x float> @llvm.x86.sse.max.ss(<4 x float>, <4 x float>)
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declare i32 @llvm.x86.sse.cvtss2si(<4 x float>)
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declare i64 @llvm.x86.sse.cvtss2si64(<4 x float>)
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declare i32 @llvm.x86.sse.cvttss2si(<4 x float>)
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declare i64 @llvm.x86.sse.cvttss2si64(<4 x float>)
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declare i32 @llvm.x86.sse2.cvtsd2si(<2 x double>)
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declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>)
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declare i32 @llvm.x86.sse2.cvttsd2si(<2 x double>)
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declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>)
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