258 lines
13 KiB
LLVM
258 lines
13 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -codegenprepare -mcpu=corei7 %s | FileCheck %s --check-prefixes=CHECK,CHECK-SSE2
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; RUN: opt -S -codegenprepare -mcpu=bdver2 %s | FileCheck %s --check-prefixes=CHECK,CHECK-XOP
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; RUN: opt -S -codegenprepare -mcpu=core-avx2 %s | FileCheck %s --check-prefixes=CHECK,CHECK-AVX,CHECK-AVX2
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; RUN: opt -S -codegenprepare -mcpu=skylake-avx512 %s | FileCheck %s --check-prefixes=CHECK,CHECK-AVX,CHECK-AVX512BW
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-darwin10.9.0"
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define <16 x i8> @test_8bit(<16 x i8> %lhs, <16 x i8> %tmp, i1 %tst) {
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; CHECK-LABEL: @test_8bit(
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; CHECK-NEXT: [[MASK:%.*]] = shufflevector <16 x i8> [[TMP:%.*]], <16 x i8> poison, <16 x i32> zeroinitializer
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; CHECK-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
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; CHECK: if_true:
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; CHECK-NEXT: ret <16 x i8> [[MASK]]
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; CHECK: if_false:
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; CHECK-NEXT: [[RES:%.*]] = shl <16 x i8> [[LHS:%.*]], [[MASK]]
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; CHECK-NEXT: ret <16 x i8> [[RES]]
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;
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%mask = shufflevector <16 x i8> %tmp, <16 x i8> poison, <16 x i32> zeroinitializer
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br i1 %tst, label %if_true, label %if_false
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if_true:
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ret <16 x i8> %mask
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if_false:
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%res = shl <16 x i8> %lhs, %mask
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ret <16 x i8> %res
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}
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define <8 x i16> @test_16bit(<8 x i16> %lhs, <8 x i16> %tmp, i1 %tst) {
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; CHECK-SSE2-LABEL: @test_16bit(
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; CHECK-SSE2-NEXT: [[MASK:%.*]] = shufflevector <8 x i16> [[TMP:%.*]], <8 x i16> poison, <8 x i32> zeroinitializer
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; CHECK-SSE2-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
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; CHECK-SSE2: if_true:
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; CHECK-SSE2-NEXT: ret <8 x i16> [[MASK]]
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; CHECK-SSE2: if_false:
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; CHECK-SSE2-NEXT: [[TMP1:%.*]] = shufflevector <8 x i16> [[TMP]], <8 x i16> poison, <8 x i32> zeroinitializer
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; CHECK-SSE2-NEXT: [[RES:%.*]] = shl <8 x i16> [[LHS:%.*]], [[TMP1]]
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; CHECK-SSE2-NEXT: ret <8 x i16> [[RES]]
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;
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; CHECK-XOP-LABEL: @test_16bit(
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; CHECK-XOP-NEXT: [[MASK:%.*]] = shufflevector <8 x i16> [[TMP:%.*]], <8 x i16> poison, <8 x i32> zeroinitializer
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; CHECK-XOP-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
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; CHECK-XOP: if_true:
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; CHECK-XOP-NEXT: ret <8 x i16> [[MASK]]
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; CHECK-XOP: if_false:
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; CHECK-XOP-NEXT: [[RES:%.*]] = shl <8 x i16> [[LHS:%.*]], [[MASK]]
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; CHECK-XOP-NEXT: ret <8 x i16> [[RES]]
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;
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; CHECK-AVX2-LABEL: @test_16bit(
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; CHECK-AVX2-NEXT: [[MASK:%.*]] = shufflevector <8 x i16> [[TMP:%.*]], <8 x i16> poison, <8 x i32> zeroinitializer
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; CHECK-AVX2-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
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; CHECK-AVX2: if_true:
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; CHECK-AVX2-NEXT: ret <8 x i16> [[MASK]]
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; CHECK-AVX2: if_false:
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; CHECK-AVX2-NEXT: [[TMP1:%.*]] = shufflevector <8 x i16> [[TMP]], <8 x i16> poison, <8 x i32> zeroinitializer
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; CHECK-AVX2-NEXT: [[RES:%.*]] = shl <8 x i16> [[LHS:%.*]], [[TMP1]]
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; CHECK-AVX2-NEXT: ret <8 x i16> [[RES]]
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;
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; CHECK-AVX512BW-LABEL: @test_16bit(
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; CHECK-AVX512BW-NEXT: [[MASK:%.*]] = shufflevector <8 x i16> [[TMP:%.*]], <8 x i16> poison, <8 x i32> zeroinitializer
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; CHECK-AVX512BW-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
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; CHECK-AVX512BW: if_true:
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; CHECK-AVX512BW-NEXT: ret <8 x i16> [[MASK]]
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; CHECK-AVX512BW: if_false:
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; CHECK-AVX512BW-NEXT: [[RES:%.*]] = shl <8 x i16> [[LHS:%.*]], [[MASK]]
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; CHECK-AVX512BW-NEXT: ret <8 x i16> [[RES]]
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;
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%mask = shufflevector <8 x i16> %tmp, <8 x i16> poison, <8 x i32> zeroinitializer
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br i1 %tst, label %if_true, label %if_false
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if_true:
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ret <8 x i16> %mask
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if_false:
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%res = shl <8 x i16> %lhs, %mask
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ret <8 x i16> %res
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}
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define <4 x i32> @test_notsplat(<4 x i32> %lhs, <4 x i32> %tmp, i1 %tst) {
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; CHECK-LABEL: @test_notsplat(
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; CHECK-NEXT: [[MASK:%.*]] = shufflevector <4 x i32> [[TMP:%.*]], <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 0>
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; CHECK-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
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; CHECK: if_true:
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; CHECK-NEXT: ret <4 x i32> [[MASK]]
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; CHECK: if_false:
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; CHECK-NEXT: [[RES:%.*]] = shl <4 x i32> [[LHS:%.*]], [[MASK]]
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; CHECK-NEXT: ret <4 x i32> [[RES]]
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;
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%mask = shufflevector <4 x i32> %tmp, <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 0>
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br i1 %tst, label %if_true, label %if_false
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if_true:
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ret <4 x i32> %mask
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if_false:
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%res = shl <4 x i32> %lhs, %mask
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ret <4 x i32> %res
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}
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define <4 x i32> @test_32bit(<4 x i32> %lhs, <4 x i32> %tmp, i1 %tst) {
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; CHECK-SSE2-LABEL: @test_32bit(
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; CHECK-SSE2-NEXT: [[MASK:%.*]] = shufflevector <4 x i32> [[TMP:%.*]], <4 x i32> poison, <4 x i32> <i32 0, i32 undef, i32 0, i32 0>
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; CHECK-SSE2-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
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; CHECK-SSE2: if_true:
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; CHECK-SSE2-NEXT: ret <4 x i32> [[MASK]]
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; CHECK-SSE2: if_false:
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; CHECK-SSE2-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[TMP]], <4 x i32> poison, <4 x i32> <i32 0, i32 undef, i32 0, i32 0>
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; CHECK-SSE2-NEXT: [[RES:%.*]] = ashr <4 x i32> [[LHS:%.*]], [[TMP1]]
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; CHECK-SSE2-NEXT: ret <4 x i32> [[RES]]
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;
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; CHECK-XOP-LABEL: @test_32bit(
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; CHECK-XOP-NEXT: [[MASK:%.*]] = shufflevector <4 x i32> [[TMP:%.*]], <4 x i32> poison, <4 x i32> <i32 0, i32 undef, i32 0, i32 0>
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; CHECK-XOP-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
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; CHECK-XOP: if_true:
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; CHECK-XOP-NEXT: ret <4 x i32> [[MASK]]
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; CHECK-XOP: if_false:
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; CHECK-XOP-NEXT: [[RES:%.*]] = ashr <4 x i32> [[LHS:%.*]], [[MASK]]
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; CHECK-XOP-NEXT: ret <4 x i32> [[RES]]
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;
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; CHECK-AVX-LABEL: @test_32bit(
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; CHECK-AVX-NEXT: [[MASK:%.*]] = shufflevector <4 x i32> [[TMP:%.*]], <4 x i32> poison, <4 x i32> <i32 0, i32 undef, i32 0, i32 0>
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; CHECK-AVX-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
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; CHECK-AVX: if_true:
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; CHECK-AVX-NEXT: ret <4 x i32> [[MASK]]
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; CHECK-AVX: if_false:
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; CHECK-AVX-NEXT: [[RES:%.*]] = ashr <4 x i32> [[LHS:%.*]], [[MASK]]
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; CHECK-AVX-NEXT: ret <4 x i32> [[RES]]
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;
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%mask = shufflevector <4 x i32> %tmp, <4 x i32> poison, <4 x i32> <i32 0, i32 undef, i32 0, i32 0>
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br i1 %tst, label %if_true, label %if_false
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if_true:
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ret <4 x i32> %mask
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if_false:
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%res = ashr <4 x i32> %lhs, %mask
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ret <4 x i32> %res
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}
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define <2 x i64> @test_64bit(<2 x i64> %lhs, <2 x i64> %tmp, i1 %tst) {
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; CHECK-SSE2-LABEL: @test_64bit(
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; CHECK-SSE2-NEXT: [[MASK:%.*]] = shufflevector <2 x i64> [[TMP:%.*]], <2 x i64> poison, <2 x i32> zeroinitializer
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; CHECK-SSE2-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
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; CHECK-SSE2: if_true:
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; CHECK-SSE2-NEXT: ret <2 x i64> [[MASK]]
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; CHECK-SSE2: if_false:
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; CHECK-SSE2-NEXT: [[TMP1:%.*]] = shufflevector <2 x i64> [[TMP]], <2 x i64> poison, <2 x i32> zeroinitializer
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; CHECK-SSE2-NEXT: [[RES:%.*]] = lshr <2 x i64> [[LHS:%.*]], [[TMP1]]
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; CHECK-SSE2-NEXT: ret <2 x i64> [[RES]]
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;
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; CHECK-XOP-LABEL: @test_64bit(
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; CHECK-XOP-NEXT: [[MASK:%.*]] = shufflevector <2 x i64> [[TMP:%.*]], <2 x i64> poison, <2 x i32> zeroinitializer
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; CHECK-XOP-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
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; CHECK-XOP: if_true:
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; CHECK-XOP-NEXT: ret <2 x i64> [[MASK]]
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; CHECK-XOP: if_false:
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; CHECK-XOP-NEXT: [[RES:%.*]] = lshr <2 x i64> [[LHS:%.*]], [[MASK]]
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; CHECK-XOP-NEXT: ret <2 x i64> [[RES]]
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;
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; CHECK-AVX-LABEL: @test_64bit(
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; CHECK-AVX-NEXT: [[MASK:%.*]] = shufflevector <2 x i64> [[TMP:%.*]], <2 x i64> poison, <2 x i32> zeroinitializer
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; CHECK-AVX-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
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; CHECK-AVX: if_true:
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; CHECK-AVX-NEXT: ret <2 x i64> [[MASK]]
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; CHECK-AVX: if_false:
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; CHECK-AVX-NEXT: [[RES:%.*]] = lshr <2 x i64> [[LHS:%.*]], [[MASK]]
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; CHECK-AVX-NEXT: ret <2 x i64> [[RES]]
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;
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%mask = shufflevector <2 x i64> %tmp, <2 x i64> poison, <2 x i32> zeroinitializer
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br i1 %tst, label %if_true, label %if_false
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if_true:
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ret <2 x i64> %mask
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if_false:
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%res = lshr <2 x i64> %lhs, %mask
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ret <2 x i64> %res
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}
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define void @funnel_splatvar(i32* nocapture %arr, i32 %rot) {
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; CHECK-SSE2-LABEL: @funnel_splatvar(
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; CHECK-SSE2-NEXT: entry:
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; CHECK-SSE2-NEXT: [[BROADCAST_SPLATINSERT15:%.*]] = insertelement <8 x i32> poison, i32 [[ROT:%.*]], i32 0
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; CHECK-SSE2-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK-SSE2: vector.body:
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; CHECK-SSE2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-SSE2-NEXT: [[T0:%.*]] = getelementptr inbounds i32, i32* [[ARR:%.*]], i64 [[INDEX]]
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; CHECK-SSE2-NEXT: [[T1:%.*]] = bitcast i32* [[T0]] to <8 x i32>*
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; CHECK-SSE2-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i32>, <8 x i32>* [[T1]], align 4
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; CHECK-SSE2-NEXT: [[TMP0:%.*]] = shufflevector <8 x i32> [[BROADCAST_SPLATINSERT15]], <8 x i32> poison, <8 x i32> zeroinitializer
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; CHECK-SSE2-NEXT: [[T2:%.*]] = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> [[WIDE_LOAD]], <8 x i32> [[WIDE_LOAD]], <8 x i32> [[TMP0]])
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; CHECK-SSE2-NEXT: store <8 x i32> [[T2]], <8 x i32>* [[T1]], align 4
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; CHECK-SSE2-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 8
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; CHECK-SSE2-NEXT: [[T3:%.*]] = icmp eq i64 [[INDEX_NEXT]], 65536
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; CHECK-SSE2-NEXT: br i1 [[T3]], label [[FOR_COND_CLEANUP:%.*]], label [[VECTOR_BODY]]
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; CHECK-SSE2: for.cond.cleanup:
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; CHECK-SSE2-NEXT: ret void
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;
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; CHECK-XOP-LABEL: @funnel_splatvar(
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; CHECK-XOP-NEXT: entry:
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; CHECK-XOP-NEXT: [[BROADCAST_SPLATINSERT15:%.*]] = insertelement <8 x i32> poison, i32 [[ROT:%.*]], i32 0
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; CHECK-XOP-NEXT: [[BROADCAST_SPLAT16:%.*]] = shufflevector <8 x i32> [[BROADCAST_SPLATINSERT15]], <8 x i32> poison, <8 x i32> zeroinitializer
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; CHECK-XOP-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK-XOP: vector.body:
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; CHECK-XOP-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-XOP-NEXT: [[T0:%.*]] = getelementptr inbounds i32, i32* [[ARR:%.*]], i64 [[INDEX]]
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; CHECK-XOP-NEXT: [[T1:%.*]] = bitcast i32* [[T0]] to <8 x i32>*
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; CHECK-XOP-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i32>, <8 x i32>* [[T1]], align 4
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; CHECK-XOP-NEXT: [[T2:%.*]] = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> [[WIDE_LOAD]], <8 x i32> [[WIDE_LOAD]], <8 x i32> [[BROADCAST_SPLAT16]])
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; CHECK-XOP-NEXT: store <8 x i32> [[T2]], <8 x i32>* [[T1]], align 4
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; CHECK-XOP-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 8
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; CHECK-XOP-NEXT: [[T3:%.*]] = icmp eq i64 [[INDEX_NEXT]], 65536
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; CHECK-XOP-NEXT: br i1 [[T3]], label [[FOR_COND_CLEANUP:%.*]], label [[VECTOR_BODY]]
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; CHECK-XOP: for.cond.cleanup:
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; CHECK-XOP-NEXT: ret void
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;
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; CHECK-AVX-LABEL: @funnel_splatvar(
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; CHECK-AVX-NEXT: entry:
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; CHECK-AVX-NEXT: [[BROADCAST_SPLATINSERT15:%.*]] = insertelement <8 x i32> poison, i32 [[ROT:%.*]], i32 0
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; CHECK-AVX-NEXT: [[BROADCAST_SPLAT16:%.*]] = shufflevector <8 x i32> [[BROADCAST_SPLATINSERT15]], <8 x i32> poison, <8 x i32> zeroinitializer
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; CHECK-AVX-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK-AVX: vector.body:
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; CHECK-AVX-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-AVX-NEXT: [[T0:%.*]] = getelementptr inbounds i32, i32* [[ARR:%.*]], i64 [[INDEX]]
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; CHECK-AVX-NEXT: [[T1:%.*]] = bitcast i32* [[T0]] to <8 x i32>*
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; CHECK-AVX-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i32>, <8 x i32>* [[T1]], align 4
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; CHECK-AVX-NEXT: [[T2:%.*]] = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> [[WIDE_LOAD]], <8 x i32> [[WIDE_LOAD]], <8 x i32> [[BROADCAST_SPLAT16]])
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; CHECK-AVX-NEXT: store <8 x i32> [[T2]], <8 x i32>* [[T1]], align 4
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; CHECK-AVX-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 8
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; CHECK-AVX-NEXT: [[T3:%.*]] = icmp eq i64 [[INDEX_NEXT]], 65536
|
||
|
|
; CHECK-AVX-NEXT: br i1 [[T3]], label [[FOR_COND_CLEANUP:%.*]], label [[VECTOR_BODY]]
|
||
|
|
; CHECK-AVX: for.cond.cleanup:
|
||
|
|
; CHECK-AVX-NEXT: ret void
|
||
|
|
;
|
||
|
|
entry:
|
||
|
|
%broadcast.splatinsert15 = insertelement <8 x i32> poison, i32 %rot, i32 0
|
||
|
|
%broadcast.splat16 = shufflevector <8 x i32> %broadcast.splatinsert15, <8 x i32> poison, <8 x i32> zeroinitializer
|
||
|
|
br label %vector.body
|
||
|
|
|
||
|
|
vector.body:
|
||
|
|
%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
|
||
|
|
%t0 = getelementptr inbounds i32, i32* %arr, i64 %index
|
||
|
|
%t1 = bitcast i32* %t0 to <8 x i32>*
|
||
|
|
%wide.load = load <8 x i32>, <8 x i32>* %t1, align 4
|
||
|
|
%t2 = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> %wide.load, <8 x i32> %wide.load, <8 x i32> %broadcast.splat16)
|
||
|
|
store <8 x i32> %t2, <8 x i32>* %t1, align 4
|
||
|
|
%index.next = add i64 %index, 8
|
||
|
|
%t3 = icmp eq i64 %index.next, 65536
|
||
|
|
br i1 %t3, label %for.cond.cleanup, label %vector.body
|
||
|
|
|
||
|
|
for.cond.cleanup:
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
declare <8 x i32> @llvm.fshl.v8i32(<8 x i32>, <8 x i32>, <8 x i32>)
|