56 lines
3.3 KiB
TableGen
56 lines
3.3 KiB
TableGen
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// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o - | FileCheck %s
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include "llvm/Target/Target.td"
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include "GlobalISelEmitterCommon.td"
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def : GINodeEquiv<G_BUILD_VECTOR, build_vector>;
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def ONE : I<(outs GPR32:$dst), (ins GPR32:$src1), []>;
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def TWO : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
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// G_BUILD_VECTOR is guaranteed to have at least one operand, therefore performing a
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// number of operands check is not needed to avoid per-operand checks accessing the
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// MI's operand list out of bounds in this particular pattern. However, we still
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// must perform the check, as a G_BUILD_VECTOR instance with two source operands
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// will pass all checks done by this pattern otherwise, which will lead to a
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// mis-match if this pattern tried first (and it will if it has higher complexity).
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def : Pat<(build_vector GPR32:$src1),
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(ONE GPR32:$src1)> {
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let AddedComplexity = 1000;
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}
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def : Pat<(build_vector GPR32:$src1, GPR32:$src2),
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(TWO GPR32:$src1, GPR32:$src2)>;
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// CHECK: GIM_Try, /*On fail goto*//*Label 0*/ [[NEXT_OPCODE_LABEL:[0-9]+]],
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// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_BUILD_VECTOR,
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// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ [[NEXT_NUM_OPERANDS_LABEL_1:[0-9]+]], // Rule ID 0 //
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// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
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// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
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// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
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// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
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// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
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// CHECK-NEXT: // (build_vector:{ *:[i32] } GPR32:{ *:[i32] }:$src1) => (ONE:{ *:[i32] } GPR32:{ *:[i32] }:$src1)
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// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::ONE,
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// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
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// CHECK-NEXT: // GIR_Coverage, 0,
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// CHECK-NEXT: GIR_Done,
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// CHECK-NEXT: // Label 1: @[[NEXT_NUM_OPERANDS_LABEL_1]]
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// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ [[NEXT_NUM_OPERANDS_LABEL_2:[0-9]+]], // Rule ID 1 //
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// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
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// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
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// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
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// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
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// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
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// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
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// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
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// CHECK-NEXT: // (build_vector:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) => (TWO:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2)
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// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::TWO,
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// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
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// CHECK-NEXT: // GIR_Coverage, 1,
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// CHECK-NEXT: GIR_Done,
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// CHECK-NEXT: // Label 2: @[[NEXT_NUM_OPERANDS_LABEL_2]]
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// CHECK-NEXT: GIM_Reject,
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// CHECK-NEXT: // Label 0: @[[NEXT_OPCODE_LABEL]]
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// CHECK-NEXT: GIM_Reject,
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