33 lines
963 B
TableGen
33 lines
963 B
TableGen
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// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s
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// Check that we don't generate invalid code of the form "( && Cond2)" when
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// emitting AssemblerPredicate conditions. In the example below, the invalid
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// code would be: "return ( && (Bits & arch::AssemblerCondition2));".
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include "llvm/Target/Target.td"
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def archInstrInfo : InstrInfo { }
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def arch : Target {
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let InstructionSet = archInstrInfo;
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}
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def AssemblerCondition2 : SubtargetFeature<"cond2", "cond2", "true", "">;
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def Pred1 : Predicate<"Condition1">;
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def Pred2 : Predicate<"Condition2">,
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AssemblerPredicate<(all_of AssemblerCondition2)>;
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def foo : Instruction {
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let Size = 2;
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let OutOperandList = (outs);
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let InOperandList = (ins);
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field bits<16> Inst;
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let Inst = 0xAAAA;
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let AsmString = "foo";
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field bits<16> SoftFail = 0;
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// This is the important bit:
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let Predicates = [Pred1, Pred2];
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}
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// CHECK: return (Bits[arch::AssemblerCondition2]);
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