46 lines
1.9 KiB
ArmAsm
46 lines
1.9 KiB
ArmAsm
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// RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+8msecext -show-encoding < %s 2>%t \
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// RUN: | FileCheck --check-prefix=CHECK %s
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// RUN: FileCheck --check-prefix=ERROR < %t %s
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// RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+8msecext -show-encoding < %s 2>%t \
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// RUN: | FileCheck --check-prefix=CHECK %s
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// RUN: FileCheck --check-prefix=ERROR < %t %s
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// RUN: not llvm-mc -triple=thumbv8.1m.main-none-none-eabi -mattr=-8msecext < %s 2>%t
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// RUN: FileCheck --check-prefix=NOSEC < %t %s
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// CHECK: vscclrm {s0, s1, s2, s3, vpr} @ encoding: [0x9f,0xec,0x04,0x0a]
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// NOSEC: instruction requires: ARMv8-M Security Extensions
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vscclrm {s0-s3, vpr}
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// CHECK: vscclrm {s3, s4, s5, s6, s7, s8, vpr} @ encoding: [0xdf,0xec,0x06,0x1a]
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// NOSEC: instruction requires: ARMv8-M Security Extensions
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vscclrm {s3-s8, vpr}
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// CHECK: vscclrm {s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, vpr} @ encoding: [0x9f,0xec,0x0c,0x9a]
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vscclrm {s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, vpr}
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// CHECK: vscclrm {s31, vpr} @ encoding: [0xdf,0xec,0x01,0xfa]
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vscclrm {s31, vpr}
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// CHECK: vscclrm {d0, d1, vpr} @ encoding: [0x9f,0xec,0x04,0x0b]
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vscclrm {d0-d1, vpr}
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// CHECK: vscclrm {d0, d1, d2, d3, vpr} @ encoding: [0x9f,0xec,0x08,0x0b]
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vscclrm {d0-d3, vpr}
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// CHECK: vscclrm {d5, d6, d7, vpr} @ encoding: [0x9f,0xec,0x06,0x5b]
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vscclrm {d5-d7, vpr}
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// CHECK: it hi @ encoding: [0x88,0xbf]
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it hi
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// CHECK: vscclrmhi {s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr} @ encoding: [0xdf,0xec,0x1d,0x1a]
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vscclrmhi {s3-s31, vpr}
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// ERROR: non-contiguous register range
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vscclrm {s0, s3-s4, vpr}
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// ERROR: register expected
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vscclrm {s32, vpr}
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// ERROR: invalid operand for instruction
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vscclrm {s0-s1}
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