190 lines
7.4 KiB
ArmAsm
190 lines
7.4 KiB
ArmAsm
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@ RUN: not llvm-mc -triple=thumbv7-apple-darwin < %s 2> %t
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@ RUN: FileCheck --check-prefix=CHECK-ERRORS --check-prefix=CHECK-ERRORS-V7 < %t %s
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@ RUN: not llvm-mc -triple=thumbv8-apple-darwin < %s 2> %t
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@ RUN: FileCheck --check-prefix=CHECK-ERRORS --check-prefix=CHECK-ERRORS-V8 < %t %s
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@ Ill-formed IT block instructions.
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itet eq
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addle r0, r1, r2
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nop
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it le
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iteeee gt
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ittfe le
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nopeq
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@ CHECK-ERRORS: error: incorrect condition in IT block; got 'le', but expected 'eq'
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@ CHECK-ERRORS: addle r0, r1, r2
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: incorrect condition in IT block; got 'al', but expected 'ne'
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@ CHECK-ERRORS: nop
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: instructions in IT block must be predicable
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@ CHECK-ERRORS: it le
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: too many conditions on IT instruction
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@ CHECK-ERRORS: iteeee gt
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: illegal IT block condition mask 'tfe'
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@ CHECK-ERRORS: ittfe le
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: predicated instructions must be in IT block
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@ CHECK-ERRORS: nopeq
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@ CHECK-ERRORS: ^
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@ Out of range immediates for MRC/MRC2/MRRC/MRRC2
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mrc p14, #8, r1, c1, c2, #4
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mrc p14, #1, r1, c1, c2, #8
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mrc2 p14, #8, r1, c1, c2, #4
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mrc2 p14, #0, r1, c1, c2, #9
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mrrc p14, #16, r5, r4, c1
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mrrc2 p14, #17, r5, r4, c1
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@ CHECK-ERRORS: operand must be an immediate in the range [0,7]
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@ CHECK-ERRORS: operand must be an immediate in the range [0,7]
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@ CHECK-ERRORS-V7: operand must be an immediate in the range [0,7]
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@ CHECK-ERRORS-V7: operand must be an immediate in the range [0,7]
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@ CHECK-ERRORS-V8: invalid instruction
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@ CHECK-ERRORS-V8: too many operands for instruction
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@ CHECK-ERRORS: operand must be an immediate in the range [0,15]
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@ CHECK-ERRORS-V7: operand must be an immediate in the range [0,15]
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@ CHECK-ERRORS-V8: invalid instruction
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isb #-1
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isb #16
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@ CHECK-ERRORS: error: immediate value out of range
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@ CHECK-ERRORS: error: immediate value out of range
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itt eq
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bkpteq #1
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@ CHECK-ERRORS: error: instruction 'bkpt' is not predicable, but condition code specified
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nopeq
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nopeq
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@ out of range operands for Thumb2 targets
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beq.w #-1048578
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bne.w #1048576
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blt.w #1013411
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b.w #-16777218
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b.w #16777216
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b.w #1592313
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@ CHECK-ERRORS: error: branch target out of range
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@ CHECK-ERRORS: error: branch target out of range
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@ CHECK-ERRORS: error: branch target out of range
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@ CHECK-ERRORS: error: branch target out of range
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@ CHECK-ERRORS: error: branch target out of range
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@ CHECK-ERRORS: error: branch target out of range
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foo2:
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movw r0, foo2
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movt r0, foo2
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movt r0, #0x10000
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movt r0, #0x10000
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@ CHECK-ERRORS: error: immediate expression for mov requires :lower16: or :upper16
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: immediate expression for mov requires :lower16: or :upper16
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: operand must be an immediate in the range [0,0xffff] or a relocatable expression
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@ CHECK-ERRORS: error: operand must be an immediate in the range [0,0xffff] or a relocatable expression
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and sp, r1, #80008000
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and pc, r1, #80008000
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@ CHECK-ERRORS: error: invalid instruction
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@ CHECK-ERRORS: error: invalid instruction
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ssat r0, #1, r0, asr #32
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usat r0, #1, r0, asr #32
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@ CHECK-ERRORS: error: 'asr #32' shift amount not allowed in Thumb mode
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@ CHECK-ERRORS: error: 'asr #32' shift amount not allowed in Thumb mode
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@ PC is not valid as shifted-rGPR
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sbc.w r2, r7, pc, lsr #16
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and.w r2, r7, pc, lsr #16
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@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
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@ CHECK-ERRORS: note: invalid operand for instruction
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@ CHECK-ERRORS-V7: note: operand must be a register in range [r0, r12] or r14
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@ CHECK-ERRORS-V8: note: operand must be a register in range [r0, r14]
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@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
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@ CHECK-ERRORS: note: invalid operand for instruction
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@ CHECK-ERRORS-V7: note: operand must be a register in range [r0, r12] or r14
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@ CHECK-ERRORS-V8: note: operand must be a register in range [r0, r14]
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@ PC is not valid as base of load
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ldr r0, [pc, r0]
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ldrb r1, [pc, r2]
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ldrh r3, [pc, r3]
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pld r4, [pc, r5]
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str r6, [pc, r7]
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strb r7 [pc, r8]
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strh r9, [pc, r10]
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@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
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@ CHECK-ERRORS: note: invalid operand for instruction
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@ CHECK-ERRORS: note: instruction requires: arm-mode
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@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
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@ CHECK-ERRORS: note: invalid operand for instruction
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@ CHECK-ERRORS: note: instruction requires: arm-mode
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@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
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@ CHECK-ERRORS: note: instruction requires: arm-mode
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@ CHECK-ERRORS: note: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid instruction
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@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
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@ CHECK-ERRORS: note: invalid operand for instruction
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@ CHECK-ERRORS: note: instruction requires: arm-mode
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@ CHECK-ERRORS: error: immediate value expected for vector index
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@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
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@ CHECK-ERRORS: note: instruction requires: arm-mode
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@ CHECK-ERRORS: note: invalid operand for instruction
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@ SWP(B) is an ARM-only instruction
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swp r0, r1, [r2]
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swpb r3, r4, [r5]
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@ CHECK-ERRORS-V7: error: instruction requires: arm-mode
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@ CHECK-ERRORS-V7: error: instruction requires: arm-mode
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@ CHECK-ERRORS-V8: error: invalid instruction
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@ CHECK-ERRORS-V8: error: invalid instruction
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@ Generic error for too few operands
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adds
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adds r0
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@ CHECK-ERRORS: error: too few operands for instruction
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@ CHECK-ERRORS: error: too few operands for instruction
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tst sp, #3
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tst sp, r5
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tst sp, r5, lsl #3
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@ CHECK-ERRORS-V7: error: operand must be a register in range [r0, r12] or r14
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@ CHECK-ERRORS-V7: operand must be a register in range [r0, r12] or r14
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@ CHECK-ERRORS-V7: operand must be a register in range [r0, r12] or r14
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teq sp, #5
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teq sp, r7
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teq sp, r9, lsl #2
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@ CHECK-ERRORS-V7: error: operand must be a register in range [r0, r12] or r14
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@ CHECK-ERRORS-V7: operand must be a register in range [r0, r12] or r14
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@ CHECK-ERRORS-V7: operand must be a register in range [r0, r12] or r14
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tbb [r0, sp]
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@ v8 allows rm = sp
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@ CHECK-ERRORS-V7: error: instruction variant requires ARMv8 or later
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tbb [r0, pc]
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@ rm = pc is always unpredictable
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@ CHECK-ERRORS: error: invalid operand for instruction
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tbb [sp, r0]
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@ v8 allows rn = sp
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@ CHECK-ERRORS-V7: error: instruction variant requires ARMv8 or later
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@ rn = pc is allowed so not included here
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tbh [r0, sp, lsl #1]
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@ v8 allows rm = sp
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@ CHECK-ERRORS-V7: error: instruction variant requires ARMv8 or later
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tbh [r0, pc, lsl #1]
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@ rm = pc is always unpredictable
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@ CHECK-ERRORS: error: invalid operand for instruction
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tbh [sp, r0, lsl #1]
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@ v8 allows rn = sp
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@ CHECK-ERRORS-V7: error: instruction variant requires ARMv8 or later
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@ rn=pc is allowed so not included here
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