35 lines
1.8 KiB
ArmAsm
35 lines
1.8 KiB
ArmAsm
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// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+i8mm < %s 2>&1 | FileCheck %s
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// No interesting edge cases for [US]MMLA, except for the fact that the data
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// types are fixed (no 64-bit version), and USMMLA exists, but SUMMLA does not.
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smmla v1.2s, v16.8b, v31.8b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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summla v1.4s, v16.16b, v31.16b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unrecognized instruction mnemonic, did you mean: smmla, ummla, usmmla?
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// USDOT (vector) has two valid data type combinations, others are rejected.
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usdot v3.4s, v15.8b, v30.8b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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usdot v3.2s, v15.16b, v30.16b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// For USDOT and SUDOT (indexed), the index is in range [0,3] (regardless of data types)
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usdot v31.2s, v1.8b, v2.4b[4]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
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usdot v31.4s, v1.16b, v2.4b[4]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
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sudot v31.2s, v1.8b, v2.4b[4]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
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sudot v31.4s, v1.16b, v2.4b[4]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
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// The arrangement specifiers of the first two operands must match.
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usdot v31.4s, v1.8b, v2.4b[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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usdot v31.2s, v1.16b, v2.4b[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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sudot v31.4s, v1.8b, v2.4b[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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sudot v31.2s, v1.16b, v2.4b[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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