38 lines
1.4 KiB
ArmAsm
38 lines
1.4 KiB
ArmAsm
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Source and Destination Registers must match
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srshlr z0.b, p0/m, z1.b, z2.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
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// CHECK-NEXT: srshlr z0.b, p0/m, z1.b, z2.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Element sizes must match
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srshlr z0.b, p0/m, z0.d, z1.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: srshlr z0.b, p0/m, z0.d, z1.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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srshlr z0.b, p0/m, z0.b, z1.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: srshlr z0.b, p0/m, z0.b, z1.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid predicate
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srshlr z0.b, p0/z, z0.b, z1.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: srshlr z0.b, p0/z, z0.b, z1.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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srshlr z0.b, p8/m, z0.b, z1.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: srshlr z0.b, p8/m, z0.b, z1.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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