104 lines
4.0 KiB
ArmAsm
104 lines
4.0 KiB
ArmAsm
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
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// ------------------------------------------------------------------------- //
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// Invalid element size
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sqrdcmlah z0.h, z1.b, z2.b[0], #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: sqrdcmlah z0.h, z1.b, z2.b[0], #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqrdcmlah z0.h, z1.s, z2.s[0], #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: sqrdcmlah z0.h, z1.s, z2.s[0], #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqrdcmlah z0.h, z1.d, z2.d[0], #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: sqrdcmlah z0.h, z1.d, z2.d[0], #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqrdcmlah z0.s, z1.b, z2.b[0], #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: sqrdcmlah z0.s, z1.b, z2.b[0], #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqrdcmlah z0.s, z1.h, z2.h[0], #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: sqrdcmlah z0.s, z1.h, z2.h[0], #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqrdcmlah z0.s, z1.d, z2.d[0], #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: sqrdcmlah z0.s, z1.d, z2.d[0], #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid restricted register for indexed vector.
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sqrdcmlah z0.h, z1.h, z8.h[3], #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: sqrdcmlah z0.h, z1.h, z8.h[3], #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqrdcmlah z0.s, z1.s, z16.s[1], #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: sqrdcmlah z0.s, z1.s, z16.s[1], #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid element index
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sqrdcmlah z0.h, z1.h, z7.h[-1], #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
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// CHECK-NEXT: sqrdcmlah z0.h, z1.h, z7.h[-1], #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqrdcmlah z0.h, z1.h, z7.h[4], #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
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// CHECK-NEXT: sqrdcmlah z0.h, z1.h, z7.h[4], #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqrdcmlah z0.s, z1.s, z15.s[-1], #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
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// CHECK-NEXT: sqrdcmlah z0.s, z1.s, z15.s[-1], #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqrdcmlah z0.s, z1.s, z15.s[2], #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
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// CHECK-NEXT: sqrdcmlah z0.s, z1.s, z15.s[2], #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid rotation
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sqrdcmlah z0.h, z1.h, z2.h[0], #360
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 0, 90, 180 or 270.
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// CHECK-NEXT: sqrdcmlah z0.h, z1.h, z2.h[0], #360
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqrdcmlah z0.s, z1.s, z2.s[0], #450
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 0, 90, 180 or 270.
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// CHECK-NEXT: sqrdcmlah z0.s, z1.s, z2.s[0], #450
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z0.b, p0/z, z7.b
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sqrdcmlah z0.b, z1.b, z31.b, #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
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// CHECK-NEXT: sqrdcmlah z0.b, z1.b, z31.b, #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z0.s, p0/z, z7.s
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sqrdcmlah z0.s, z1.s, z15.s[1], #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
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// CHECK-NEXT: sqrdcmlah z0.s, z1.s, z15.s[1], #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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