85 lines
3.1 KiB
ArmAsm
85 lines
3.1 KiB
ArmAsm
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
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// ------------------------------------------------------------------------- //
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// Invalid element widths.
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ext z0.h, { z1.h, z2.h }, #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: ext z0.h, { z1.h, z2.h }, #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ext z0.s, { z1.s, z2.s }, #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: ext z0.s, { z1.s, z2.s }, #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ext z0.d, { z1.d, z2.d }, #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: ext z0.d, { z1.d, z2.d }, #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid immediate range.
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ext z0.b, { z1.b, z2.b }, #-1
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255].
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// CHECK-NEXT: ext z0.b, { z1.b, z2.b }, #-1
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ext z0.b, { z1.b, z2.b }, #256
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255].
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// CHECK-NEXT: ext z0.b, { z1.b, z2.b }, #256
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector list.
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ext z0.b, { }, #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
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// CHECK-NEXT: ext z0.b, { }, #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ext z0.b, { z1.b }, #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: ext z0.b, { z1.b }, #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ext z0.b, { z1.b, z2.b, z3.b }, #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: ext z0.b, { z1.b, z2.b, z3.b }, #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ext z0.b, { z1.b, z2.h }, #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
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// CHECK-NEXT: ext z0.b, { z1.b, z2.h }, #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ext z0.b, { z1.b, z31.b }, #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
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// CHECK-NEXT: ext z0.b, { z1.b, z31.b }, #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ext z0.b, { v0.4b, v1.4b }, #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: ext z0.b, { v0.4b, v1.4b }, #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z31, z6
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ext z31.b, { z30.b, z31.b }, #255
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: ext z31.b, { z30.b, z31.b }, #255
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z31.b, p0/z, z6.b
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ext z31.b, { z30.b, z31.b }, #255
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: ext z31.b, { z30.b, z31.b }, #255
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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