42 lines
1.5 KiB
ArmAsm
42 lines
1.5 KiB
ArmAsm
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// Element size specifiers should match.
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sxth z0.d, p0/m, z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: sxth z0.d, p0/m, z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// Missing predicate suffix
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sxth z29.d, p7, z29.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: sxth z29.d, p7, z29.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Unsupported element widths
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sxth z0.b, p0/m, z0.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: sxth z0.b, p0/m, z0.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sxth z0.h, p0/m, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: sxth z0.h, p0/m, z0.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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sxth z0.s, p8/m, z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: sxth z0.s, p8/m, z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sxth z0.d, p8/m, z0.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: sxth z0.d, p8/m, z0.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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