337 lines
10 KiB
ArmAsm
337 lines
10 KiB
ArmAsm
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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// ---------------------------------------------------------------------------//
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// Test 64-bit form (x0) and its aliases
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// ---------------------------------------------------------------------------//
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sqincw x0
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// CHECK-INST: sqincw x0
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// CHECK-ENCODING: [0xe0,0xf3,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 f3 b0 04 <unknown>
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sqincw x0, all
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// CHECK-INST: sqincw x0
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// CHECK-ENCODING: [0xe0,0xf3,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 f3 b0 04 <unknown>
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sqincw x0, all, mul #1
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// CHECK-INST: sqincw x0
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// CHECK-ENCODING: [0xe0,0xf3,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 f3 b0 04 <unknown>
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sqincw x0, all, mul #16
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// CHECK-INST: sqincw x0, all, mul #16
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// CHECK-ENCODING: [0xe0,0xf3,0xbf,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 f3 bf 04 <unknown>
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// ---------------------------------------------------------------------------//
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// Test 32-bit form (x0, w0) and its aliases
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// ---------------------------------------------------------------------------//
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sqincw x0, w0
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// CHECK-INST: sqincw x0, w0
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// CHECK-ENCODING: [0xe0,0xf3,0xa0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 f3 a0 04 <unknown>
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sqincw x0, w0, all
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// CHECK-INST: sqincw x0, w0
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// CHECK-ENCODING: [0xe0,0xf3,0xa0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 f3 a0 04 <unknown>
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sqincw x0, w0, all, mul #1
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// CHECK-INST: sqincw x0, w0
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// CHECK-ENCODING: [0xe0,0xf3,0xa0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 f3 a0 04 <unknown>
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sqincw x0, w0, all, mul #16
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// CHECK-INST: sqincw x0, w0, all, mul #16
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// CHECK-ENCODING: [0xe0,0xf3,0xaf,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 f3 af 04 <unknown>
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sqincw x0, w0, pow2
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// CHECK-INST: sqincw x0, w0, pow2
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// CHECK-ENCODING: [0x00,0xf0,0xa0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 f0 a0 04 <unknown>
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sqincw x0, w0, pow2, mul #16
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// CHECK-INST: sqincw x0, w0, pow2, mul #16
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// CHECK-ENCODING: [0x00,0xf0,0xaf,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 f0 af 04 <unknown>
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// ---------------------------------------------------------------------------//
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// Test vector form and aliases.
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// ---------------------------------------------------------------------------//
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sqincw z0.s
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// CHECK-INST: sqincw z0.s
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// CHECK-ENCODING: [0xe0,0xc3,0xa0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 c3 a0 04 <unknown>
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sqincw z0.s, all
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// CHECK-INST: sqincw z0.s
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// CHECK-ENCODING: [0xe0,0xc3,0xa0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 c3 a0 04 <unknown>
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sqincw z0.s, all, mul #1
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// CHECK-INST: sqincw z0.s
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// CHECK-ENCODING: [0xe0,0xc3,0xa0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 c3 a0 04 <unknown>
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sqincw z0.s, all, mul #16
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// CHECK-INST: sqincw z0.s, all, mul #16
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// CHECK-ENCODING: [0xe0,0xc3,0xaf,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 c3 af 04 <unknown>
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sqincw z0.s, pow2
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// CHECK-INST: sqincw z0.s, pow2
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// CHECK-ENCODING: [0x00,0xc0,0xa0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 c0 a0 04 <unknown>
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sqincw z0.s, pow2, mul #16
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// CHECK-INST: sqincw z0.s, pow2, mul #16
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// CHECK-ENCODING: [0x00,0xc0,0xaf,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 c0 af 04 <unknown>
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// ---------------------------------------------------------------------------//
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// Test all patterns for 64-bit form
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// ---------------------------------------------------------------------------//
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sqincw x0, pow2
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// CHECK-INST: sqincw x0, pow2
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// CHECK-ENCODING: [0x00,0xf0,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 f0 b0 04 <unknown>
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sqincw x0, vl1
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// CHECK-INST: sqincw x0, vl1
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// CHECK-ENCODING: [0x20,0xf0,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 20 f0 b0 04 <unknown>
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sqincw x0, vl2
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// CHECK-INST: sqincw x0, vl2
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// CHECK-ENCODING: [0x40,0xf0,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 40 f0 b0 04 <unknown>
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sqincw x0, vl3
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// CHECK-INST: sqincw x0, vl3
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// CHECK-ENCODING: [0x60,0xf0,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 60 f0 b0 04 <unknown>
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sqincw x0, vl4
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// CHECK-INST: sqincw x0, vl4
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// CHECK-ENCODING: [0x80,0xf0,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 80 f0 b0 04 <unknown>
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sqincw x0, vl5
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// CHECK-INST: sqincw x0, vl5
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// CHECK-ENCODING: [0xa0,0xf0,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: a0 f0 b0 04 <unknown>
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sqincw x0, vl6
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// CHECK-INST: sqincw x0, vl6
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// CHECK-ENCODING: [0xc0,0xf0,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: c0 f0 b0 04 <unknown>
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sqincw x0, vl7
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// CHECK-INST: sqincw x0, vl7
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// CHECK-ENCODING: [0xe0,0xf0,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 f0 b0 04 <unknown>
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sqincw x0, vl8
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// CHECK-INST: sqincw x0, vl8
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// CHECK-ENCODING: [0x00,0xf1,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 f1 b0 04 <unknown>
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sqincw x0, vl16
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// CHECK-INST: sqincw x0, vl16
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// CHECK-ENCODING: [0x20,0xf1,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 20 f1 b0 04 <unknown>
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sqincw x0, vl32
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// CHECK-INST: sqincw x0, vl32
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// CHECK-ENCODING: [0x40,0xf1,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 40 f1 b0 04 <unknown>
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sqincw x0, vl64
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// CHECK-INST: sqincw x0, vl64
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// CHECK-ENCODING: [0x60,0xf1,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 60 f1 b0 04 <unknown>
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sqincw x0, vl128
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// CHECK-INST: sqincw x0, vl128
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// CHECK-ENCODING: [0x80,0xf1,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 80 f1 b0 04 <unknown>
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sqincw x0, vl256
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// CHECK-INST: sqincw x0, vl256
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// CHECK-ENCODING: [0xa0,0xf1,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: a0 f1 b0 04 <unknown>
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sqincw x0, #14
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// CHECK-INST: sqincw x0, #14
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// CHECK-ENCODING: [0xc0,0xf1,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: c0 f1 b0 04 <unknown>
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sqincw x0, #15
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// CHECK-INST: sqincw x0, #15
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// CHECK-ENCODING: [0xe0,0xf1,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 f1 b0 04 <unknown>
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sqincw x0, #16
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// CHECK-INST: sqincw x0, #16
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// CHECK-ENCODING: [0x00,0xf2,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 f2 b0 04 <unknown>
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sqincw x0, #17
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// CHECK-INST: sqincw x0, #17
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// CHECK-ENCODING: [0x20,0xf2,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 20 f2 b0 04 <unknown>
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sqincw x0, #18
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// CHECK-INST: sqincw x0, #18
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// CHECK-ENCODING: [0x40,0xf2,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 40 f2 b0 04 <unknown>
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sqincw x0, #19
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// CHECK-INST: sqincw x0, #19
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// CHECK-ENCODING: [0x60,0xf2,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 60 f2 b0 04 <unknown>
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sqincw x0, #20
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// CHECK-INST: sqincw x0, #20
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// CHECK-ENCODING: [0x80,0xf2,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 80 f2 b0 04 <unknown>
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sqincw x0, #21
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// CHECK-INST: sqincw x0, #21
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// CHECK-ENCODING: [0xa0,0xf2,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: a0 f2 b0 04 <unknown>
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sqincw x0, #22
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// CHECK-INST: sqincw x0, #22
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// CHECK-ENCODING: [0xc0,0xf2,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: c0 f2 b0 04 <unknown>
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sqincw x0, #23
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// CHECK-INST: sqincw x0, #23
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// CHECK-ENCODING: [0xe0,0xf2,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 f2 b0 04 <unknown>
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sqincw x0, #24
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// CHECK-INST: sqincw x0, #24
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// CHECK-ENCODING: [0x00,0xf3,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 f3 b0 04 <unknown>
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sqincw x0, #25
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// CHECK-INST: sqincw x0, #25
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// CHECK-ENCODING: [0x20,0xf3,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 20 f3 b0 04 <unknown>
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sqincw x0, #26
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// CHECK-INST: sqincw x0, #26
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// CHECK-ENCODING: [0x40,0xf3,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 40 f3 b0 04 <unknown>
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sqincw x0, #27
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// CHECK-INST: sqincw x0, #27
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// CHECK-ENCODING: [0x60,0xf3,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 60 f3 b0 04 <unknown>
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sqincw x0, #28
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// CHECK-INST: sqincw x0, #28
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// CHECK-ENCODING: [0x80,0xf3,0xb0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 80 f3 b0 04 <unknown>
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// --------------------------------------------------------------------------//
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// Test compatibility with MOVPRFX instruction.
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movprfx z0, z7
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// CHECK-INST: movprfx z0, z7
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// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
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sqincw z0.s
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// CHECK-INST: sqincw z0.s
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// CHECK-ENCODING: [0xe0,0xc3,0xa0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 c3 a0 04 <unknown>
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movprfx z0, z7
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// CHECK-INST: movprfx z0, z7
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// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
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sqincw z0.s, pow2, mul #16
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// CHECK-INST: sqincw z0.s, pow2, mul #16
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// CHECK-ENCODING: [0x00,0xc0,0xaf,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 c0 af 04 <unknown>
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movprfx z0, z7
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// CHECK-INST: movprfx z0, z7
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// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
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sqincw z0.s, pow2
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// CHECK-INST: sqincw z0.s, pow2
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||
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// CHECK-ENCODING: [0x00,0xc0,0xa0,0x04]
|
||
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// CHECK-ERROR: instruction requires: sve
|
||
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// CHECK-UNKNOWN: 00 c0 a0 04 <unknown>
|