48 lines
1.9 KiB
ArmAsm
48 lines
1.9 KiB
ArmAsm
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// ------------------------------------------------------------------------- //
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// Tied operands must match
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splice z0.b, p0, z1.b, z2.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
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// CHECK-NEXT: splice z0.b, p0, z1.b, z2.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid element widths.
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splice z0.b, p0, z0.b, z2.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: splice z0.b, p0, z0.b, z2.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid predicate
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splice z0.b, p8, z0.b, z1.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: splice z0.b, p8, z0.b, z1.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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splice z0.b, p7.b, z0.b, z1.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: splice z0.b, p7.b, z0.b, z1.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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splice z0.b, p7.q, z0.b, z1.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: splice z0.b, p7.q, z0.b, z1.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z4.d, p7/z, z6.d
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splice z4.d, p7, z4.d, z31.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
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// CHECK-NEXT: splice z4.d, p7, z4.d, z31.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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