90 lines
3.4 KiB
ArmAsm
90 lines
3.4 KiB
ArmAsm
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Immediate not compatible with encode/decode function.
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orn z5.b, z5.b, #0xfa
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
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// CHECK-NEXT: orn z5.b, z5.b, #0xfa
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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orn z5.b, z5.b, #0xfff9
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
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// CHECK-NEXT: orn z5.b, z5.b, #0xfff9
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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orn z5.h, z5.h, #0xfffa
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
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// CHECK-NEXT: orn z5.h, z5.h, #0xfffa
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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orn z5.h, z5.h, #0xfffffff9
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
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// CHECK-NEXT: orn z5.h, z5.h, #0xfffffff9
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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orn z5.s, z5.s, #0xfffffffa
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
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// CHECK-NEXT: orn z5.s, z5.s, #0xfffffffa
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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orn z5.s, z5.s, #0xffffffffffffff9
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
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// CHECK-NEXT: orn z5.s, z5.s, #0xffffffffffffff9
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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orn z15.d, z15.d, #0xfffffffffffffffa
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
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// CHECK-NEXT: orn z15.d, z15.d, #0xfffffffffffffffa
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Source and Destination Registers must match
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orn z7.d, z8.d, #254
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
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// CHECK-NEXT: orn z7.d, z8.d, #254
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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orn z7.d, z8.d, #254
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
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// CHECK-NEXT: orn z7.d, z8.d, #254
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Predicate register must have .b suffix
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orn p0.h, p0/z, p0.h, p1.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
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// CHECK-NEXT: orn p0.h, p0/z, p0.h, p1.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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orn p0.s, p0/z, p0.s, p1.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
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// CHECK-NEXT: orn p0.s, p0/z, p0.s, p1.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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orn p0.d, p0/z, p0.d, p1.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
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// CHECK-NEXT: orn p0.d, p0/z, p0.d, p1.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Operation only has zeroing predicate behaviour (p0/z).
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orn p0.b, p0/m, p1.b, p2.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: orn p0.b, p0/m, p1.b, p2.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z0.d, p0/z, z7.d
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orn z0.d, z0.d, #0x6
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
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// CHECK-NEXT: orn z0.d, z0.d, #0x6
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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