180 lines
7.0 KiB
ArmAsm
180 lines
7.0 KiB
ArmAsm
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid operand (.s)
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ld1sw z23.s, p0/z, [x13, #1, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: ld1sw z23.s, p0/z, [x13, #1, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sw z29.s, p0/z, [x3, #1, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: ld1sw z29.s, p0/z, [x3, #1, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Immediate out of lower bound [-8, 7].
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ld1sw z28.d, p2/z, [x28, #-9, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
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// CHECK-NEXT: ld1sw z28.d, p2/z, [x28, #-9, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sw z27.d, p1/z, [x26, #8, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
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// CHECK-NEXT: ld1sw z27.d, p1/z, [x26, #8, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// restricted predicate has range [0, 7].
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ld1sw z4.d, p8/z, [x11, #1, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: ld1sw z4.d, p8/z, [x11, #1, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector list.
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ld1sw { }, p0/z, [x1, #1, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
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// CHECK-NEXT: ld1sw { }, p0/z, [x1, #1, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sw { z1.d, z2.d }, p0/z, [x1, #1, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: ld1sw { z1.d, z2.d }, p0/z, [x1, #1, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sw { v0.2d }, p0/z, [x1, #1, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: ld1sw { v0.2d }, p0/z, [x1, #1, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid scalar + scalar addressing modes
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ld1sw z0.d, p0/z, [x0, x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
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// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sw z0.d, p0/z, [x0, xzr]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
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// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, xzr]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sw z0.d, p0/z, [x0, x0, lsl #3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
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// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, x0, lsl #3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sw z0.d, p0/z, [x0, w0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
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// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, w0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sw z0.d, p0/z, [x0, w0, uxtw]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
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// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, w0, uxtw]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid scalar + vector addressing modes
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ld1sw z0.d, p0/z, [x0, z0.h]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.h]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sw z0.d, p0/z, [x0, z0.s]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.s]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sw z0.d, p0/z, [x0, z0.d, uxtw #3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
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// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, uxtw #3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sw z0.d, p0/z, [x0, z0.d, lsl #3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
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// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, lsl #3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sw z0.d, p0/z, [x0, z0.d, lsl]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected #imm after shift specifier
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// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, lsl]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sw z0.d, p0/z, [x0, z0.d, lsl #3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
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// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, lsl #3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sw z0.d, p0/z, [x0, z0.d, sxtw #3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
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// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, sxtw #3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector + immediate addressing modes
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ld1sw z0.s, p0/z, [z0.s]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: ld1sw z0.s, p0/z, [z0.s]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sw z0.s, p0/z, [z0.s, #4]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: ld1sw z0.s, p0/z, [z0.s, #4]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sw z0.d, p0/z, [z0.d, #-4]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
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// CHECK-NEXT: ld1sw z0.d, p0/z, [z0.d, #-4]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sw z0.d, p0/z, [z0.d, #-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
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// CHECK-NEXT: ld1sw z0.d, p0/z, [z0.d, #-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sw z0.d, p0/z, [z0.d, #125]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
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// CHECK-NEXT: ld1sw z0.d, p0/z, [z0.d, #125]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sw z0.d, p0/z, [z0.d, #128]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
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// CHECK-NEXT: ld1sw z0.d, p0/z, [z0.d, #128]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sw z0.d, p0/z, [z0.d, #3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
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// CHECK-NEXT: ld1sw z0.d, p0/z, [z0.d, #3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z0.d, p0/z, z7.d
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ld1sw { z0.d }, p0/z, [z0.d]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: ld1sw { z0.d }, p0/z, [z0.d]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z0, z7
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ld1sw { z0.d }, p0/z, [z0.d]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: ld1sw { z0.d }, p0/z, [z0.d]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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