127 lines
4.3 KiB
ArmAsm
127 lines
4.3 KiB
ArmAsm
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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fsubr z0.h, p0/m, z0.h, #0.500000000000000
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// CHECK-INST: fsubr z0.h, p0/m, z0.h, #0.5
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// CHECK-ENCODING: [0x00,0x80,0x5b,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 80 5b 65 <unknown>
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fsubr z0.h, p0/m, z0.h, #0.5
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// CHECK-INST: fsubr z0.h, p0/m, z0.h, #0.5
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// CHECK-ENCODING: [0x00,0x80,0x5b,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 80 5b 65 <unknown>
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fsubr z0.s, p0/m, z0.s, #0.5
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// CHECK-INST: fsubr z0.s, p0/m, z0.s, #0.5
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// CHECK-ENCODING: [0x00,0x80,0x9b,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 80 9b 65 <unknown>
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fsubr z0.d, p0/m, z0.d, #0.5
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// CHECK-INST: fsubr z0.d, p0/m, z0.d, #0.5
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// CHECK-ENCODING: [0x00,0x80,0xdb,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 80 db 65 <unknown>
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fsubr z31.h, p7/m, z31.h, #1.000000000000000
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// CHECK-INST: fsubr z31.h, p7/m, z31.h, #1.0
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// CHECK-ENCODING: [0x3f,0x9c,0x5b,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 3f 9c 5b 65 <unknown>
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fsubr z31.h, p7/m, z31.h, #1.0
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// CHECK-INST: fsubr z31.h, p7/m, z31.h, #1.0
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// CHECK-ENCODING: [0x3f,0x9c,0x5b,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 3f 9c 5b 65 <unknown>
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fsubr z31.s, p7/m, z31.s, #1.0
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// CHECK-INST: fsubr z31.s, p7/m, z31.s, #1.0
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// CHECK-ENCODING: [0x3f,0x9c,0x9b,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 3f 9c 9b 65 <unknown>
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fsubr z31.d, p7/m, z31.d, #1.0
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// CHECK-INST: fsubr z31.d, p7/m, z31.d, #1.0
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// CHECK-ENCODING: [0x3f,0x9c,0xdb,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 3f 9c db 65 <unknown>
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fsubr z0.h, p7/m, z0.h, z31.h
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// CHECK-INST: fsubr z0.h, p7/m, z0.h, z31.h
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// CHECK-ENCODING: [0xe0,0x9f,0x43,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 9f 43 65 <unknown>
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fsubr z0.s, p7/m, z0.s, z31.s
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// CHECK-INST: fsubr z0.s, p7/m, z0.s, z31.s
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// CHECK-ENCODING: [0xe0,0x9f,0x83,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 9f 83 65 <unknown>
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fsubr z0.d, p7/m, z0.d, z31.d
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// CHECK-INST: fsubr z0.d, p7/m, z0.d, z31.d
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// CHECK-ENCODING: [0xe0,0x9f,0xc3,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 9f c3 65 <unknown>
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// --------------------------------------------------------------------------//
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// Test compatibility with MOVPRFX instruction.
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movprfx z31.d, p7/z, z6.d
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// CHECK-INST: movprfx z31.d, p7/z, z6.d
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// CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: df 3c d0 04 <unknown>
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fsubr z31.d, p7/m, z31.d, #1.0
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// CHECK-INST: fsubr z31.d, p7/m, z31.d, #1.0
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// CHECK-ENCODING: [0x3f,0x9c,0xdb,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 3f 9c db 65 <unknown>
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movprfx z31, z6
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// CHECK-INST: movprfx z31, z6
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// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: df bc 20 04 <unknown>
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fsubr z31.d, p7/m, z31.d, #1.0
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// CHECK-INST: fsubr z31.d, p7/m, z31.d, #1.0
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// CHECK-ENCODING: [0x3f,0x9c,0xdb,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 3f 9c db 65 <unknown>
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movprfx z0.d, p7/z, z7.d
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// CHECK-INST: movprfx z0.d, p7/z, z7.d
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// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
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fsubr z0.d, p7/m, z0.d, z31.d
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// CHECK-INST: fsubr z0.d, p7/m, z0.d, z31.d
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// CHECK-ENCODING: [0xe0,0x9f,0xc3,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 9f c3 65 <unknown>
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movprfx z0, z7
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// CHECK-INST: movprfx z0, z7
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// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
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fsubr z0.d, p7/m, z0.d, z31.d
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// CHECK-INST: fsubr z0.d, p7/m, z0.d, z31.d
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// CHECK-ENCODING: [0xe0,0x9f,0xc3,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 9f c3 65 <unknown>
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