175 lines
5.8 KiB
ArmAsm
175 lines
5.8 KiB
ArmAsm
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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fmul z0.h, p0/m, z0.h, #0.5000000000000
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// CHECK-INST: fmul z0.h, p0/m, z0.h, #0.5
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// CHECK-ENCODING: [0x00,0x80,0x5a,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 80 5a 65 <unknown>
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fmul z0.h, p0/m, z0.h, #0.5
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// CHECK-INST: fmul z0.h, p0/m, z0.h, #0.5
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// CHECK-ENCODING: [0x00,0x80,0x5a,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 80 5a 65 <unknown>
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fmul z0.s, p0/m, z0.s, #0.5
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// CHECK-INST: fmul z0.s, p0/m, z0.s, #0.5
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// CHECK-ENCODING: [0x00,0x80,0x9a,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 80 9a 65 <unknown>
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fmul z0.d, p0/m, z0.d, #0.5
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// CHECK-INST: fmul z0.d, p0/m, z0.d, #0.5
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// CHECK-ENCODING: [0x00,0x80,0xda,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 80 da 65 <unknown>
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fmul z31.h, p7/m, z31.h, #2.0
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// CHECK-INST: fmul z31.h, p7/m, z31.h, #2.0
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// CHECK-ENCODING: [0x3f,0x9c,0x5a,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 3f 9c 5a 65 <unknown>
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fmul z31.s, p7/m, z31.s, #2.0
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// CHECK-INST: fmul z31.s, p7/m, z31.s, #2.0
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// CHECK-ENCODING: [0x3f,0x9c,0x9a,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 3f 9c 9a 65 <unknown>
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fmul z31.d, p7/m, z31.d, #2.0
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// CHECK-INST: fmul z31.d, p7/m, z31.d, #2.0
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// CHECK-ENCODING: [0x3f,0x9c,0xda,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 3f 9c da 65 <unknown>
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fmul z0.h, z0.h, z0.h[0]
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// CHECK-INST: fmul z0.h, z0.h, z0.h[0]
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// CHECK-ENCODING: [0x00,0x20,0x20,0x64]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 20 20 64 <unknown>
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fmul z0.s, z0.s, z0.s[0]
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// CHECK-INST: fmul z0.s, z0.s, z0.s[0]
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// CHECK-ENCODING: [0x00,0x20,0xa0,0x64]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 20 a0 64 <unknown>
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fmul z0.d, z0.d, z0.d[0]
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// CHECK-INST: fmul z0.d, z0.d, z0.d[0]
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// CHECK-ENCODING: [0x00,0x20,0xe0,0x64]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 20 e0 64 <unknown>
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fmul z31.h, z31.h, z7.h[7]
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// CHECK-INST: fmul z31.h, z31.h, z7.h[7]
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// CHECK-ENCODING: [0xff,0x23,0x7f,0x64]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 23 7f 64 <unknown>
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fmul z31.s, z31.s, z7.s[3]
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// CHECK-INST: fmul z31.s, z31.s, z7.s[3]
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// CHECK-ENCODING: [0xff,0x23,0xbf,0x64]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 23 bf 64 <unknown>
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fmul z31.d, z31.d, z15.d[1]
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// CHECK-INST: fmul z31.d, z31.d, z15.d[1]
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// CHECK-ENCODING: [0xff,0x23,0xff,0x64]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 23 ff 64 <unknown>
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fmul z0.h, p7/m, z0.h, z31.h
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// CHECK-INST: fmul z0.h, p7/m, z0.h, z31.h
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// CHECK-ENCODING: [0xe0,0x9f,0x42,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 9f 42 65 <unknown>
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fmul z0.s, p7/m, z0.s, z31.s
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// CHECK-INST: fmul z0.s, p7/m, z0.s, z31.s
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// CHECK-ENCODING: [0xe0,0x9f,0x82,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 9f 82 65 <unknown>
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fmul z0.d, p7/m, z0.d, z31.d
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// CHECK-INST: fmul z0.d, p7/m, z0.d, z31.d
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// CHECK-ENCODING: [0xe0,0x9f,0xc2,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 9f c2 65 <unknown>
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fmul z0.h, z1.h, z31.h
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// CHECK-INST: fmul z0.h, z1.h, z31.h
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// CHECK-ENCODING: [0x20,0x08,0x5f,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 20 08 5f 65 <unknown>
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fmul z0.s, z1.s, z31.s
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// CHECK-INST: fmul z0.s, z1.s, z31.s
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// CHECK-ENCODING: [0x20,0x08,0x9f,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 20 08 9f 65 <unknown>
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fmul z0.d, z1.d, z31.d
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// CHECK-INST: fmul z0.d, z1.d, z31.d
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// CHECK-ENCODING: [0x20,0x08,0xdf,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 20 08 df 65 <unknown>
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// --------------------------------------------------------------------------//
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// Test compatibility with MOVPRFX instruction.
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movprfx z31.d, p7/z, z6.d
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// CHECK-INST: movprfx z31.d, p7/z, z6.d
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// CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: df 3c d0 04 <unknown>
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fmul z31.d, p7/m, z31.d, #2.0
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// CHECK-INST: fmul z31.d, p7/m, z31.d, #2.0
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// CHECK-ENCODING: [0x3f,0x9c,0xda,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 3f 9c da 65 <unknown>
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movprfx z31, z6
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// CHECK-INST: movprfx z31, z6
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// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: df bc 20 04 <unknown>
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fmul z31.d, p7/m, z31.d, #2.0
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// CHECK-INST: fmul z31.d, p7/m, z31.d, #2.0
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// CHECK-ENCODING: [0x3f,0x9c,0xda,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 3f 9c da 65 <unknown>
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movprfx z0.d, p7/z, z7.d
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// CHECK-INST: movprfx z0.d, p7/z, z7.d
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// CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
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fmul z0.d, p7/m, z0.d, z31.d
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// CHECK-INST: fmul z0.d, p7/m, z0.d, z31.d
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// CHECK-ENCODING: [0xe0,0x9f,0xc2,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 9f c2 65 <unknown>
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movprfx z0, z7
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// CHECK-INST: movprfx z0, z7
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// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
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fmul z0.d, p7/m, z0.d, z31.d
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// CHECK-INST: fmul z0.d, p7/m, z0.d, z31.d
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// CHECK-ENCODING: [0xe0,0x9f,0xc2,0x65]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: e0 9f c2 65 <unknown>
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