43 lines
1.4 KiB
ArmAsm
43 lines
1.4 KiB
ArmAsm
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// RUN: not llvm-mc -o - -triple=aarch64 -mattr=+sve,bf16 2>&1 %s | FileCheck %s
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bfmlalb z0.S, z1.H, z7.H[8]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
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// CHECK-NEXT: bfmlalb z0.S, z1.H, z7.H[8]
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// CHECK-NEXT: ^
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bfmlalb z0.S, z1.H, z8.H[7]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: bfmlalb z0.S, z1.H, z8.H[7]
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// CHECK-NEXT: ^
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bfmlalt z0.S, z1.H, z7.H[8]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
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// CHECK-NEXT: bfmlalt z0.S, z1.H, z7.H[8]
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// CHECK-NEXT: ^
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bfmlalt z0.S, z1.H, z8.H[7]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: bfmlalt z0.S, z1.H, z8.H[7]
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// CHECK-NEXT: ^
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bfmlalt z0.S, z1.H, z7.2h[2]
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// CHECK: error: invalid vector kind qualifier
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// CHECK-NEXT: bfmlalt z0.S, z1.H, z7.2h[2]
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// CHECK-NEXT: ^
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bfmlalt z0.S, z1.H, z2.s[2]
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// CHECK: error: Invalid restricted vector register, expected z0.h..z7.h
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// CHECK-NEXT: bfmlalt z0.S, z1.H, z2.s[2]
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// CHECK-NEXT: ^
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bfmlalt z0.S, z1.s, z2.h[2]
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// CHECK: error: invalid element width
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// CHECK-NEXT: bfmlalt z0.S, z1.s, z2.h[2]
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// CHECK-NEXT: ^
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movprfx z0.s, p0/m, z7.s
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bfmlalt z0.s, z1.h, z2.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx
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// CHECK-NEXT: bfmlalt z0.s, z1.h, z2.h
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// CHECK-NEXT: ^
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