28 lines
1.0 KiB
ArmAsm
28 lines
1.0 KiB
ArmAsm
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// RUN: not llvm-mc -triple=aarch64 -mattr=+sve,bf16 2>&1 < %s| FileCheck %s
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bfcvt z0.s, p0/m, z1.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: bfcvt z0.s, p0/m, z1.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfcvt z0.h, p0/m, z1.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: bfcvt z0.h, p0/m, z1.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfcvt z0.h, p0/z, z1.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: bfcvt z0.h, p0/z, z1.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfcvt z0.h, p8/m, z1.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: bfcvt z0.h, p8/m, z1.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z0.h, p0/m, z7.h
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bfcvt z0.h, p0/m, z1.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx with a different element size
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// CHECK-NEXT: bfcvt z0.h, p0/m, z1.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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