354 lines
8.1 KiB
Plaintext
354 lines
8.1 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s
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--- |
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define i64 @test_sext_i1(i8 %a) {
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%val = trunc i8 %a to i1
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%r = sext i1 %val to i64
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ret i64 %r
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}
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define i64 @test_sext_i8(i8 %val) {
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%r = sext i8 %val to i64
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ret i64 %r
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}
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define i64 @test_sext_i16(i16 %val) {
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%r = sext i16 %val to i64
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ret i64 %r
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}
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define i64 @test_sext_i32(i32 %val) {
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%r = sext i32 %val to i64
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ret i64 %r
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}
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define i64 @test_zext_i1(i8 %a) {
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%val = trunc i8 %a to i1
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%r = zext i1 %val to i64
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ret i64 %r
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}
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define i64 @test_zext_i8(i8 %val) {
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%r = zext i8 %val to i64
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ret i64 %r
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}
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define i64 @test_zext_i16(i16 %val) {
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%r = zext i16 %val to i64
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ret i64 %r
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}
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define i64 @test_zext_i32(i32 %val) {
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%r = zext i32 %val to i64
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ret i64 %r
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}
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define void @test_anyext_i1(i8 %a) {
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ret void
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}
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define void @test_anyext_i8(i8 %val) {
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ret void
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}
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define void @test_anyext_i16(i16 %val) {
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ret void
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}
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define void @test_anyext_i32(i32 %val) {
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ret void
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}
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...
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---
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name: test_sext_i1
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; CHECK-LABEL: name: test_sext_i1
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; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s8)
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; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 63
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; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C]](s8)
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; CHECK: [[COPY1:%[0-9]+]]:_(s8) = COPY [[C]](s8)
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; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s8)
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; CHECK: $rax = COPY [[ASHR]](s64)
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; CHECK: RET 0, implicit $rax
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%0(s8) = COPY $dil
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%1(s1) = G_TRUNC %0(s8)
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%2(s64) = G_SEXT %1(s1)
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$rax = COPY %2(s64)
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RET 0, implicit $rax
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...
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---
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name: test_sext_i8
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; CHECK-LABEL: name: test_sext_i8
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; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
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; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s8)
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; CHECK: $rax = COPY [[SEXT]](s64)
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; CHECK: RET 0, implicit $rax
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%0(s8) = COPY $dil
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%1(s64) = G_SEXT %0(s8)
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$rax = COPY %1(s64)
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RET 0, implicit $rax
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...
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---
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name: test_sext_i16
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; CHECK-LABEL: name: test_sext_i16
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; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY $di
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; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s16)
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; CHECK: $rax = COPY [[SEXT]](s64)
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; CHECK: RET 0, implicit $rax
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%0(s16) = COPY $di
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%1(s64) = G_SEXT %0(s16)
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$rax = COPY %1(s64)
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RET 0, implicit $rax
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...
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---
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name: test_sext_i32
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; CHECK-LABEL: name: test_sext_i32
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
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; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s32)
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; CHECK: $rax = COPY [[SEXT]](s64)
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; CHECK: RET 0, implicit $rax
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%0(s32) = COPY $edi
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%1(s64) = G_SEXT %0(s32)
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$rax = COPY %1(s64)
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RET 0, implicit $rax
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...
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---
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name: test_zext_i1
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; CHECK-LABEL: name: test_zext_i1
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; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s8)
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; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
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; CHECK: $rax = COPY [[AND]](s64)
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; CHECK: RET 0, implicit $rax
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%0(s8) = COPY $dil
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%1(s1) = G_TRUNC %0(s8)
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%2(s64) = G_ZEXT %1(s1)
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$rax = COPY %2(s64)
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RET 0, implicit $rax
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...
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---
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name: test_zext_i8
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; CHECK-LABEL: name: test_zext_i8
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; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
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; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s8)
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; CHECK: $rax = COPY [[ZEXT]](s64)
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; CHECK: RET 0, implicit $rax
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%0(s8) = COPY $dil
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%1(s64) = G_ZEXT %0(s8)
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$rax = COPY %1(s64)
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RET 0, implicit $rax
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...
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---
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name: test_zext_i16
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; CHECK-LABEL: name: test_zext_i16
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; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY $di
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; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s16)
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; CHECK: $rax = COPY [[ZEXT]](s64)
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; CHECK: RET 0, implicit $rax
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%0(s16) = COPY $di
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%1(s64) = G_ZEXT %0(s16)
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$rax = COPY %1(s64)
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RET 0, implicit $rax
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...
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---
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name: test_zext_i32
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; CHECK-LABEL: name: test_zext_i32
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
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; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
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; CHECK: $rax = COPY [[ZEXT]](s64)
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; CHECK: RET 0, implicit $rax
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%0(s32) = COPY $edi
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%1(s64) = G_ZEXT %0(s32)
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$rax = COPY %1(s64)
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RET 0, implicit $rax
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...
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---
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name: test_anyext_i1
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; CHECK-LABEL: name: test_anyext_i1
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; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s8)
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; CHECK: $rax = COPY [[ANYEXT]](s64)
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; CHECK: RET 0, implicit $rax
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%0(s8) = COPY $dil
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%1(s1) = G_TRUNC %0(s8)
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%2(s64) = G_ANYEXT %1(s1)
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$rax = COPY %2(s64)
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RET 0, implicit $rax
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...
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---
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name: test_anyext_i8
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; CHECK-LABEL: name: test_anyext_i8
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; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s8)
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; CHECK: $rax = COPY [[ANYEXT]](s64)
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; CHECK: RET 0, implicit $rax
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%0(s8) = COPY $dil
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%1(s64) = G_ANYEXT %0(s8)
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$rax = COPY %1(s64)
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RET 0, implicit $rax
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...
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---
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name: test_anyext_i16
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; CHECK-LABEL: name: test_anyext_i16
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; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY $di
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s16)
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; CHECK: $rax = COPY [[ANYEXT]](s64)
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; CHECK: RET 0, implicit $rax
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%0(s16) = COPY $di
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%1(s64) = G_ANYEXT %0(s16)
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$rax = COPY %1(s64)
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RET 0, implicit $rax
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...
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---
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name: test_anyext_i32
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alignment: 16
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; CHECK-LABEL: name: test_anyext_i32
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
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; CHECK: $rax = COPY [[ANYEXT]](s64)
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; CHECK: RET 0, implicit $rax
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%0(s32) = COPY $edi
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%1(s64) = G_ANYEXT %0(s32)
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$rax = COPY %1(s64)
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RET 0, implicit $rax
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...
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