61 lines
1.7 KiB
LLVM
61 lines
1.7 KiB
LLVM
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; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
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;;; Test prefetch vector intrinsic instructions
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;;;
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;;; Note:
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;;; We test PFCHVrrl, PFCHVirl, PFCHVNCrrl, and PFCHVNCirl instructions.
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; Function Attrs: nounwind
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define void @pfchv_vssl(i8* %0, i64 %1) {
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; CHECK-LABEL: pfchv_vssl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s2, 256
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; CHECK-NEXT: lvl %s2
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; CHECK-NEXT: pfchv %s1, %s0
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; CHECK-NEXT: b.l.t (, %s10)
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tail call void @llvm.ve.vl.pfchv.ssl(i64 %1, i8* %0, i32 256)
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ret void
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}
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; Function Attrs: inaccessiblemem_or_argmemonly nounwind
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declare void @llvm.ve.vl.pfchv.ssl(i64, i8*, i32)
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; Function Attrs: nounwind
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define void @pfchv_vssl_imm(i8* %0) {
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; CHECK-LABEL: pfchv_vssl_imm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: pfchv 8, %s0
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; CHECK-NEXT: b.l.t (, %s10)
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tail call void @llvm.ve.vl.pfchv.ssl(i64 8, i8* %0, i32 256)
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ret void
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}
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; Function Attrs: nounwind
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define void @pfchvnc_vssl(i8* %0, i64 %1) {
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; CHECK-LABEL: pfchvnc_vssl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s2, 256
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; CHECK-NEXT: lvl %s2
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; CHECK-NEXT: pfchv.nc %s1, %s0
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; CHECK-NEXT: b.l.t (, %s10)
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tail call void @llvm.ve.vl.pfchvnc.ssl(i64 %1, i8* %0, i32 256)
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ret void
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}
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; Function Attrs: inaccessiblemem_or_argmemonly nounwind
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declare void @llvm.ve.vl.pfchvnc.ssl(i64, i8*, i32)
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; Function Attrs: nounwind
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define void @pfchvnc_vssl_imm(i8* %0) {
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; CHECK-LABEL: pfchvnc_vssl_imm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: pfchv.nc 8, %s0
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; CHECK-NEXT: b.l.t (, %s10)
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tail call void @llvm.ve.vl.pfchvnc.ssl(i64 8, i8* %0, i32 256)
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ret void
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}
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