221 lines
6.8 KiB
LLVM
221 lines
6.8 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: opt -instcombine -mtriple=thumbv8.1m.main %s | llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - | FileCheck %s
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declare <16 x i1> @llvm.arm.mve.vctp8(i32)
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declare <8 x i1> @llvm.arm.mve.vctp16(i32)
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declare <4 x i1> @llvm.arm.mve.vctp32(i32)
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declare <4 x i1> @llvm.arm.mve.vctp64(i32)
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declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>)
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declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>)
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declare i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1>)
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declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
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declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)
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declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)
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define arm_aapcs_vfpcc zeroext i16 @test_vctp8q(i32 %a) {
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; CHECK-LABEL: test_vctp8q:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vctp.8 r0
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; CHECK-NEXT: vmrs r0, p0
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %a)
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%1 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %0)
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%2 = trunc i32 %1 to i16
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ret i16 %2
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}
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define arm_aapcs_vfpcc zeroext i16 @test_vctp8q_m(i32 %a, i16 zeroext %p) {
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; CHECK-LABEL: test_vctp8q_m:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vctpt.8 r0
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; CHECK-NEXT: vmrs r0, p0
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
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%2 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %a)
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%3 = and <16 x i1> %1, %2
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%4 = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %3)
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%5 = trunc i32 %4 to i16
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ret i16 %5
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}
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define arm_aapcs_vfpcc zeroext i16 @test_vctp16q(i32 %a) {
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; CHECK-LABEL: test_vctp16q:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vctp.16 r0
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; CHECK-NEXT: vmrs r0, p0
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %a)
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%1 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %0)
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%2 = trunc i32 %1 to i16
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ret i16 %2
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}
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define arm_aapcs_vfpcc zeroext i16 @test_vctp16q_m(i32 %a, i16 zeroext %p) {
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; CHECK-LABEL: test_vctp16q_m:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vctpt.16 r0
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; CHECK-NEXT: vmrs r0, p0
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
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%2 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %a)
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%3 = and <8 x i1> %1, %2
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%4 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %3)
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%5 = trunc i32 %4 to i16
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ret i16 %5
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}
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define arm_aapcs_vfpcc zeroext i16 @test_vctp32q(i32 %a) {
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; CHECK-LABEL: test_vctp32q:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vctp.32 r0
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; CHECK-NEXT: vmrs r0, p0
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %a)
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%1 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %0)
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%2 = trunc i32 %1 to i16
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ret i16 %2
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}
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define arm_aapcs_vfpcc zeroext i16 @test_vctp32q_m(i32 %a, i16 zeroext %p) {
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; CHECK-LABEL: test_vctp32q_m:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vctpt.32 r0
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; CHECK-NEXT: vmrs r0, p0
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
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%2 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %a)
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%3 = and <4 x i1> %1, %2
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%4 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %3)
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%5 = trunc i32 %4 to i16
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ret i16 %5
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}
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define arm_aapcs_vfpcc zeroext i16 @test_vctp64q(i32 %a) {
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; CHECK-LABEL: test_vctp64q:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vctp.64 r0
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; CHECK-NEXT: vmrs r0, p0
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <4 x i1> @llvm.arm.mve.vctp64(i32 %a)
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%1 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %0)
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%2 = trunc i32 %1 to i16
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ret i16 %2
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}
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define arm_aapcs_vfpcc zeroext i16 @test_vctp64q_m(i32 %a, i16 zeroext %p) {
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; CHECK-LABEL: test_vctp64q_m:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vctpt.64 r0
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; CHECK-NEXT: vmrs r0, p0
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
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%2 = call <4 x i1> @llvm.arm.mve.vctp64(i32 %a)
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%3 = and <4 x i1> %1, %2
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%4 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %3)
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%5 = trunc i32 %4 to i16
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ret i16 %5
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}
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define arm_aapcs_vfpcc <16 x i8> @test_vpselq_i8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) #2 {
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; CHECK-LABEL: test_vpselq_i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
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%2 = select <16 x i1> %1, <16 x i8> %a, <16 x i8> %b
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ret <16 x i8> %2
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}
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define arm_aapcs_vfpcc <8 x i16> @test_vpselq_i16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) #2 {
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; CHECK-LABEL: test_vpselq_i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
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%2 = select <8 x i1> %1, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %2
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}
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define arm_aapcs_vfpcc <8 x half> @test_vpselq_f16(<8 x half> %a, <8 x half> %b, i16 zeroext %p) #2 {
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; CHECK-LABEL: test_vpselq_f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
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%2 = select <8 x i1> %1, <8 x half> %a, <8 x half> %b
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ret <8 x half> %2
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}
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define arm_aapcs_vfpcc <4 x i32> @test_vpselq_i32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) #2 {
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; CHECK-LABEL: test_vpselq_i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
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%2 = select <4 x i1> %1, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %2
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}
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define arm_aapcs_vfpcc <4 x float> @test_vpselq_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) #2 {
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; CHECK-LABEL: test_vpselq_f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
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%2 = select <4 x i1> %1, <4 x float> %a, <4 x float> %b
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ret <4 x float> %2
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}
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define arm_aapcs_vfpcc <2 x i64> @test_vpselq_i64(<2 x i64> %a, <2 x i64> %b, i16 zeroext %p) #2 {
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; CHECK-LABEL: test_vpselq_i64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
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%2 = bitcast <2 x i64> %a to <4 x i32>
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%3 = bitcast <2 x i64> %b to <4 x i32>
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%4 = select <4 x i1> %1, <4 x i32> %2, <4 x i32> %3
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%5 = bitcast <4 x i32> %4 to <2 x i64>
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ret <2 x i64> %5
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}
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