147 lines
5.9 KiB
Plaintext
147 lines
5.9 KiB
Plaintext
|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||
|
|
# RUN: llc -mtriple=thumbv8.1m.main -mattr=+lob %s -run-pass=arm-low-overhead-loops --verify-machineinstrs -o - | FileCheck %s
|
||
|
|
|
||
|
|
# TODO: Remove the lr = tMOVr which actually makes the WLS def dead!
|
||
|
|
|
||
|
|
--- |
|
||
|
|
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
|
||
|
|
target triple = "thumbv8.1m.main"
|
||
|
|
|
||
|
|
define dso_local arm_aapcscc void @copy(i16* nocapture %a, i16* nocapture readonly %b, i32 %N) {
|
||
|
|
entry:
|
||
|
|
%0 = call i1 @llvm.test.set.loop.iterations.i32(i32 %N)
|
||
|
|
br i1 %0, label %while.body.preheader, label %while.end
|
||
|
|
|
||
|
|
while.body.preheader: ; preds = %entry
|
||
|
|
%scevgep = getelementptr i16, i16* %a, i32 -1
|
||
|
|
%scevgep3 = getelementptr i16, i16* %b, i32 -1
|
||
|
|
br label %while.body
|
||
|
|
|
||
|
|
while.body: ; preds = %while.body, %while.body.preheader
|
||
|
|
%lsr.iv4 = phi i16* [ %scevgep3, %while.body.preheader ], [ %scevgep5, %while.body ]
|
||
|
|
%lsr.iv = phi i16* [ %scevgep, %while.body.preheader ], [ %scevgep1, %while.body ]
|
||
|
|
%1 = phi i32 [ %3, %while.body ], [ %N, %while.body.preheader ]
|
||
|
|
%scevgep7 = getelementptr i16, i16* %lsr.iv, i32 1
|
||
|
|
%scevgep4 = getelementptr i16, i16* %lsr.iv4, i32 1
|
||
|
|
%2 = load i16, i16* %scevgep4, align 2
|
||
|
|
store i16 %2, i16* %scevgep7, align 2
|
||
|
|
%3 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %1, i32 1)
|
||
|
|
%4 = icmp ne i32 %3, 0
|
||
|
|
%scevgep1 = getelementptr i16, i16* %lsr.iv, i32 1
|
||
|
|
%scevgep5 = getelementptr i16, i16* %lsr.iv4, i32 1
|
||
|
|
br i1 %4, label %while.body, label %while.end
|
||
|
|
|
||
|
|
while.end: ; preds = %while.body, %entry
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
declare i1 @llvm.test.set.loop.iterations.i32(i32) #0
|
||
|
|
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0
|
||
|
|
|
||
|
|
attributes #0 = { noduplicate nounwind }
|
||
|
|
attributes #1 = { nounwind }
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: copy
|
||
|
|
alignment: 2
|
||
|
|
exposesReturnsTwice: false
|
||
|
|
legalized: false
|
||
|
|
regBankSelected: false
|
||
|
|
selected: false
|
||
|
|
failedISel: false
|
||
|
|
tracksRegLiveness: true
|
||
|
|
hasWinCFI: false
|
||
|
|
registers: []
|
||
|
|
liveins:
|
||
|
|
- { reg: '$r0', virtual-reg: '' }
|
||
|
|
- { reg: '$r1', virtual-reg: '' }
|
||
|
|
- { reg: '$r2', virtual-reg: '' }
|
||
|
|
frameInfo:
|
||
|
|
isFrameAddressTaken: false
|
||
|
|
isReturnAddressTaken: false
|
||
|
|
hasStackMap: false
|
||
|
|
hasPatchPoint: false
|
||
|
|
stackSize: 8
|
||
|
|
offsetAdjustment: 0
|
||
|
|
maxAlignment: 4
|
||
|
|
adjustsStack: false
|
||
|
|
hasCalls: false
|
||
|
|
stackProtector: ''
|
||
|
|
maxCallFrameSize: 0
|
||
|
|
cvBytesOfCalleeSavedRegisters: 0
|
||
|
|
hasOpaqueSPAdjustment: false
|
||
|
|
hasVAStart: false
|
||
|
|
hasMustTailInVarArgFunc: false
|
||
|
|
localFrameSize: 0
|
||
|
|
savePoint: ''
|
||
|
|
restorePoint: ''
|
||
|
|
fixedStack: []
|
||
|
|
stack:
|
||
|
|
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
|
||
|
|
stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
|
||
|
|
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||
|
|
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
|
||
|
|
stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
|
||
|
|
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||
|
|
callSites: []
|
||
|
|
constants: []
|
||
|
|
machineFunctionInfo: {}
|
||
|
|
body: |
|
||
|
|
; CHECK-LABEL: name: copy
|
||
|
|
; CHECK: bb.0.entry:
|
||
|
|
; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000)
|
||
|
|
; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
|
||
|
|
; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
|
||
|
|
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
|
||
|
|
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
|
||
|
|
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
|
||
|
|
; CHECK: dead $lr = t2WLS $r2, %bb.3
|
||
|
|
; CHECK: bb.1.while.body.preheader:
|
||
|
|
; CHECK: successors: %bb.2(0x80000000)
|
||
|
|
; CHECK: liveins: $r0, $r1, $r2
|
||
|
|
; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 2, 14 /* CC::al */, $noreg
|
||
|
|
; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 2, 14 /* CC::al */, $noreg
|
||
|
|
; CHECK: $lr = tMOVr killed $r2, 14 /* CC::al */, $noreg
|
||
|
|
; CHECK: bb.2.while.body:
|
||
|
|
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
|
||
|
|
; CHECK: liveins: $lr, $r0, $r1
|
||
|
|
; CHECK: renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14 /* CC::al */, $noreg :: (load 2 from %ir.scevgep4)
|
||
|
|
; CHECK: early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14 /* CC::al */, $noreg :: (store 2 into %ir.scevgep7)
|
||
|
|
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
|
||
|
|
; CHECK: bb.3.while.end:
|
||
|
|
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
|
||
|
|
bb.0.entry:
|
||
|
|
successors: %bb.1(0x40000000), %bb.3(0x40000000)
|
||
|
|
liveins: $r0, $r1, $r2, $r7, $lr
|
||
|
|
|
||
|
|
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
|
||
|
|
frame-setup CFI_INSTRUCTION def_cfa_offset 8
|
||
|
|
frame-setup CFI_INSTRUCTION offset $lr, -4
|
||
|
|
frame-setup CFI_INSTRUCTION offset $r7, -8
|
||
|
|
t2WhileLoopStart $r2, %bb.3, implicit-def dead $cpsr
|
||
|
|
tB %bb.1, 14, $noreg
|
||
|
|
|
||
|
|
bb.1.while.body.preheader:
|
||
|
|
successors: %bb.2(0x80000000)
|
||
|
|
liveins: $r0, $r1, $r2
|
||
|
|
|
||
|
|
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 2, 14, $noreg
|
||
|
|
renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 2, 14, $noreg
|
||
|
|
$lr = tMOVr killed $r2, 14, $noreg
|
||
|
|
|
||
|
|
bb.2.while.body:
|
||
|
|
successors: %bb.2(0x7c000000), %bb.3(0x04000000)
|
||
|
|
liveins: $lr, $r0, $r1
|
||
|
|
|
||
|
|
renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14, $noreg :: (load 2 from %ir.scevgep4)
|
||
|
|
early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14, $noreg :: (store 2 into %ir.scevgep7)
|
||
|
|
renamable $lr = t2LoopDec killed renamable $lr, 1
|
||
|
|
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
|
||
|
|
tB %bb.3, 14, $noreg
|
||
|
|
|
||
|
|
bb.3.while.end:
|
||
|
|
tPOP_RET 14, $noreg, def $r7, def $pc
|
||
|
|
|
||
|
|
...
|