208 lines
10 KiB
Plaintext
208 lines
10 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s
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# This example is actually equivalent as there's a sub in the loop, which is
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# then used by the add in the exit - making the vctp operands equivalent.
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--- |
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define dso_local i32 @wrong_vctp_liveout(i16* nocapture readonly %a, i16* nocapture readonly %b, i32 %N) local_unnamed_addr #0 {
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entry:
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%cmp9 = icmp eq i32 %N, 0
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%0 = add i32 %N, 3
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%1 = lshr i32 %0, 2
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%2 = shl nuw i32 %1, 2
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%3 = add i32 %2, -4
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%4 = lshr i32 %3, 2
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%5 = add nuw nsw i32 %4, 1
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br i1 %cmp9, label %for.cond.cleanup, label %vector.ph
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vector.ph: ; preds = %entry
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%start = call i32 @llvm.start.loop.iterations.i32(i32 %5)
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]
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%lsr.iv18 = phi i16* [ %scevgep19, %vector.body ], [ %b, %vector.ph ]
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%lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ]
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%vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %12, %vector.body ]
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%6 = phi i32 [ %N, %vector.ph ], [ %8, %vector.body ]
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%lsr.iv17 = bitcast i16* %lsr.iv to <4 x i16>*
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%lsr.iv1820 = bitcast i16* %lsr.iv18 to <4 x i16>*
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%7 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %6)
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%8 = sub i32 %6, 4
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%wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17, i32 2, <4 x i1> %7, <4 x i16> undef)
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%9 = sext <4 x i16> %wide.masked.load to <4 x i32>
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%wide.masked.load14 = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv1820, i32 2, <4 x i1> %7, <4 x i16> undef)
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%10 = sext <4 x i16> %wide.masked.load14 to <4 x i32>
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%11 = mul nsw <4 x i32> %10, %9
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%12 = add <4 x i32> %11, %vec.phi
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%scevgep = getelementptr i16, i16* %lsr.iv, i32 4
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%scevgep19 = getelementptr i16, i16* %lsr.iv18, i32 4
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%13 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)
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%14 = icmp ne i32 %13, 0
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%lsr.iv.next = add nsw i32 %lsr.iv1, -1
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br i1 %14, label %vector.body, label %middle.block
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middle.block: ; preds = %vector.body
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%15 = add i32 %8, 4
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%16 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %15)
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%17 = select <4 x i1> %16, <4 x i32> %12, <4 x i32> %vec.phi
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%18 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %17)
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br label %for.cond.cleanup
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for.cond.cleanup: ; preds = %middle.block, %entry
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%res.0.lcssa = phi i32 [ 0, %entry ], [ %18, %middle.block ]
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ret i32 %res.0.lcssa
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}
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declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>)
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declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
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declare i32 @llvm.start.loop.iterations.i32(i32)
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declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
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declare <4 x i1> @llvm.arm.mve.vctp32(i32)
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...
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---
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name: wrong_vctp_liveout
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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- { reg: '$r2', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 8
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: wrong_vctp_liveout
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; CHECK: bb.0.entry:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
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; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: t2IT 0, 4, implicit-def $itstate
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; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
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; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
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; CHECK: bb.1.vector.ph:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
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; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
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; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
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; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
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; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1
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; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
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; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
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; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
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; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
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; CHECK: dead $lr = t2DLS renamable $r12
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; CHECK: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg
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; CHECK: bb.2.vector.body:
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; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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; CHECK: liveins: $q1, $r0, $r1, $r2, $r3
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; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
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; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0
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; CHECK: MVE_VPST 4, implicit $vpr
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; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2)
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; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2)
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; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg
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; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
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; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg
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; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
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; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1
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; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2
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; CHECK: bb.3.middle.block:
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; CHECK: liveins: $q0, $q1, $r2
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; CHECK: renamable $r0, dead $cpsr = tADDi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg
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; CHECK: renamable $vpr = MVE_VCTP32 killed renamable $r0, 0, $noreg
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; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr
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; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
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; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
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bb.0.entry:
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successors: %bb.1(0x80000000)
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liveins: $r0, $r1, $r2, $lr, $r7
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tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr
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t2IT 0, 4, implicit-def $itstate
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renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate
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tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate
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bb.1.vector.ph:
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successors: %bb.2(0x80000000)
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liveins: $r0, $r1, $r2, $lr, $r7
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frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
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frame-setup CFI_INSTRUCTION def_cfa_offset 8
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r7, -8
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renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg
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renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1
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renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg
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renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg
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renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg
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renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg
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$lr = t2DoLoopStart renamable $r12
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$r3 = tMOVr killed $r12, 14, $noreg
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bb.2.vector.body:
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successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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liveins: $q1, $r0, $r1, $r2, $r3
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renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
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$q0 = MVE_VORR killed $q1, $q1, 0, $noreg, undef $q0
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MVE_VPST 4, implicit $vpr
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renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2)
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renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2)
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$lr = tMOVr $r3, 14, $noreg
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renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
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renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14, $noreg
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renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
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renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1
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renamable $lr = t2LoopDec killed renamable $lr, 1
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t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
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tB %bb.3, 14, $noreg
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bb.3.middle.block:
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liveins: $q0, $q1, $r2
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renamable $r0, dead $cpsr = tADDi3 killed renamable $r2, 4, 14, $noreg
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renamable $vpr = MVE_VCTP32 killed renamable $r0, 0, $noreg
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renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr
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renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
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tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
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...
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