327 lines
16 KiB
Plaintext
327 lines
16 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
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--- |
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define dso_local arm_aapcs_vfpcc void @remove_mov_lr_chain(float* nocapture readonly %pSrc, float* nocapture %pDst, i32 %blockSize) #0 {
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entry:
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%cmp5 = icmp eq i32 %blockSize, 0
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br i1 %cmp5, label %while.end, label %while.body.preheader
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while.body.preheader: ; preds = %entry
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%min.iters.check = icmp ult i32 %blockSize, 4
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br i1 %min.iters.check, label %while.body.preheader19, label %vector.memcheck
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vector.memcheck: ; preds = %while.body.preheader
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%scevgep = getelementptr float, float* %pDst, i32 %blockSize
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%scevgep12 = getelementptr float, float* %pSrc, i32 %blockSize
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%bound0 = icmp ugt float* %scevgep12, %pDst
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%bound1 = icmp ugt float* %scevgep, %pSrc
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%found.conflict = and i1 %bound0, %bound1
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%0 = lshr i32 %blockSize, 2
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%1 = shl nuw i32 %0, 2
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%2 = add i32 %1, -4
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%3 = lshr i32 %2, 2
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%4 = add nuw nsw i32 %3, 1
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br i1 %found.conflict, label %while.body.preheader19, label %vector.ph
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vector.ph: ; preds = %vector.memcheck
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%n.vec = and i32 %blockSize, -4
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%ind.end = sub i32 %blockSize, %n.vec
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%ind.end15 = getelementptr float, float* %pSrc, i32 %n.vec
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%ind.end17 = getelementptr float, float* %pDst, i32 %n.vec
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%scevgep9 = getelementptr float, float* %pDst, i32 -4
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%scevgep14 = getelementptr float, float* %pSrc, i32 -4
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%start1 = call i32 @llvm.start.loop.iterations.i32(i32 %4)
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%lsr.iv15 = phi float* [ %scevgep16, %vector.body ], [ %scevgep14, %vector.ph ]
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%lsr.iv10 = phi float* [ %scevgep11, %vector.body ], [ %scevgep9, %vector.ph ]
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%5 = phi i32 [ %start1, %vector.ph ], [ %7, %vector.body ]
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%lsr.iv1517 = bitcast float* %lsr.iv15 to <4 x float>*
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%lsr.iv1012 = bitcast float* %lsr.iv10 to <4 x float>*
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%scevgep18 = getelementptr <4 x float>, <4 x float>* %lsr.iv1517, i32 1
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%wide.load = load <4 x float>, <4 x float>* %scevgep18, align 4
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%6 = call fast <4 x float> @llvm.fabs.v4f32(<4 x float> %wide.load)
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%scevgep13 = getelementptr <4 x float>, <4 x float>* %lsr.iv1012, i32 1
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store <4 x float> %6, <4 x float>* %scevgep13, align 4
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%scevgep11 = getelementptr float, float* %lsr.iv10, i32 4
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%scevgep16 = getelementptr float, float* %lsr.iv15, i32 4
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%7 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1)
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%8 = icmp ne i32 %7, 0
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br i1 %8, label %vector.body, label %middle.block
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middle.block: ; preds = %vector.body
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%cmp.n = icmp eq i32 %n.vec, %blockSize
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br i1 %cmp.n, label %while.end, label %while.body.preheader19
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while.body.preheader19: ; preds = %middle.block, %vector.memcheck, %while.body.preheader
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%blkCnt.08.ph = phi i32 [ %blockSize, %vector.memcheck ], [ %blockSize, %while.body.preheader ], [ %ind.end, %middle.block ]
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%pSrc.addr.07.ph = phi float* [ %pSrc, %vector.memcheck ], [ %pSrc, %while.body.preheader ], [ %ind.end15, %middle.block ]
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%pDst.addr.06.ph = phi float* [ %pDst, %vector.memcheck ], [ %pDst, %while.body.preheader ], [ %ind.end17, %middle.block ]
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%scevgep1 = getelementptr float, float* %pSrc.addr.07.ph, i32 -1
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%scevgep4 = getelementptr float, float* %pDst.addr.06.ph, i32 -1
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%start2 = call i32 @llvm.start.loop.iterations.i32(i32 %blkCnt.08.ph)
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br label %while.body
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while.body: ; preds = %while.body, %while.body.preheader19
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%lsr.iv5 = phi float* [ %scevgep6, %while.body ], [ %scevgep4, %while.body.preheader19 ]
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%lsr.iv = phi float* [ %scevgep2, %while.body ], [ %scevgep1, %while.body.preheader19 ]
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%9 = phi i32 [ %start2, %while.body.preheader19 ], [ %12, %while.body ]
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%scevgep3 = getelementptr float, float* %lsr.iv, i32 1
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%scevgep7 = getelementptr float, float* %lsr.iv5, i32 1
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%10 = load float, float* %scevgep3, align 4
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%11 = tail call fast float @llvm.fabs.f32(float %10)
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store float %11, float* %scevgep7, align 4
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%scevgep2 = getelementptr float, float* %lsr.iv, i32 1
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%scevgep6 = getelementptr float, float* %lsr.iv5, i32 1
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%12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %9, i32 1)
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%13 = icmp ne i32 %12, 0
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br i1 %13, label %while.body, label %while.end
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while.end: ; preds = %while.body, %middle.block, %entry
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ret void
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}
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declare float @llvm.fabs.f32(float)
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declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
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declare i32 @llvm.start.loop.iterations.i32(i32)
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declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
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...
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---
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name: remove_mov_lr_chain
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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- { reg: '$r2', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 16
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: remove_mov_lr_chain
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; CHECK: bb.0.entry:
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; CHECK: successors: %bb.9(0x30000000), %bb.1(0x50000000)
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; CHECK: liveins: $lr, $r0, $r1, $r2, $r4, $r5, $r7
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; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
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; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
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; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12
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; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16
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; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: tBcc %bb.9, 0 /* CC::eq */, killed $cpsr
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; CHECK: bb.1.while.body.preheader:
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; CHECK: successors: %bb.6(0x40000000), %bb.2(0x40000000)
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; CHECK: liveins: $r0, $r1, $r2
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; CHECK: tCMPi8 renamable $r2, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: tBcc %bb.6, 3 /* CC::lo */, killed $cpsr
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; CHECK: bb.2.vector.memcheck:
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; CHECK: successors: %bb.3(0x40000000), %bb.6(0x40000000)
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; CHECK: liveins: $r0, $r1, $r2
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; CHECK: renamable $r3 = t2ADDrs renamable $r0, renamable $r2, 18, 14 /* CC::al */, $noreg, $noreg
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; CHECK: tCMPr killed renamable $r3, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: t2IT 8, 4, implicit-def $itstate
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; CHECK: renamable $r3 = t2ADDrs renamable $r1, renamable $r2, 18, 8 /* CC::hi */, $cpsr, $noreg, implicit $itstate
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; CHECK: tCMPr killed renamable $r3, renamable $r0, 8 /* CC::hi */, killed $cpsr, implicit-def $cpsr, implicit killed $itstate
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; CHECK: tBcc %bb.6, 8 /* CC::hi */, killed $cpsr
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; CHECK: bb.3.vector.ph:
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; CHECK: successors: %bb.4(0x80000000)
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; CHECK: liveins: $r0, $r1, $r2
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; CHECK: renamable $r4 = t2BICri renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg
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; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
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; CHECK: renamable $r12 = t2SUBri renamable $r4, 4, 14 /* CC::al */, $noreg, $noreg
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; CHECK: renamable $r7, dead $cpsr = tSUBrr renamable $r2, renamable $r4, 14 /* CC::al */, $noreg
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; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
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; CHECK: renamable $r12 = t2ADDrs renamable $r0, renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg
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; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
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; CHECK: $r5 = tMOVr killed $r3, 14 /* CC::al */, $noreg
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; CHECK: renamable $r3 = t2ADDrs renamable $r1, renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg
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; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
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; CHECK: bb.4.vector.body:
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; CHECK: successors: %bb.4(0x7c000000), %bb.5(0x04000000)
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; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $r12
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; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_pre killed renamable $r0, 16, 0, $noreg :: (load 16 from %ir.scevgep18, align 4)
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; CHECK: $lr = tMOVr killed $r5, 14 /* CC::al */, $noreg
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; CHECK: renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VABSf32 killed renamable $q0, 0, $noreg, undef renamable $q0
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; CHECK: renamable $r1 = MVE_VSTRBU8_pre killed renamable $q0, killed renamable $r1, 16, 0, $noreg :: (store 16 into %ir.scevgep13, align 4)
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; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
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; CHECK: $r5 = tMOVr killed $lr, 14 /* CC::al */, $noreg
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; CHECK: tBcc %bb.4, 1 /* CC::ne */, killed $cpsr
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; CHECK: tB %bb.5, 14 /* CC::al */, $noreg
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; CHECK: bb.5.middle.block:
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; CHECK: successors: %bb.7(0x80000000)
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; CHECK: liveins: $r2, $r3, $r4, $r7, $r12
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; CHECK: tCMPr killed renamable $r4, killed renamable $r2, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: $lr = tMOVr killed $r7, 14 /* CC::al */, $noreg
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; CHECK: t2IT 0, 8, implicit-def $itstate
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; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $r5, def $r7, def $pc, implicit killed $itstate
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; CHECK: tB %bb.7, 14 /* CC::al */, $noreg
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; CHECK: bb.6:
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; CHECK: successors: %bb.7(0x80000000)
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; CHECK: liveins: $r0, $r1, $r2
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; CHECK: $lr = tMOVr killed $r2, 14 /* CC::al */, $noreg
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; CHECK: $r12 = tMOVr killed $r0, 14 /* CC::al */, $noreg
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; CHECK: $r3 = tMOVr killed $r1, 14 /* CC::al */, $noreg
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; CHECK: bb.7.while.body.preheader19:
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; CHECK: successors: %bb.8(0x80000000)
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; CHECK: liveins: $lr, $r3, $r12
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; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r3, 4, 14 /* CC::al */, $noreg
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; CHECK: renamable $r1 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $lr = t2DLS killed renamable $lr
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; CHECK: bb.8.while.body:
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; CHECK: successors: %bb.8(0x7c000000), %bb.9(0x04000000)
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; CHECK: liveins: $lr, $r0, $r1
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; CHECK: renamable $s0 = VLDRS renamable $r1, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep3)
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; CHECK: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
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; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VABSS killed renamable $s0, 14 /* CC::al */, $noreg
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; CHECK: VSTRS killed renamable $s0, renamable $r0, 1, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep7)
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; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg
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; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.8
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; CHECK: bb.9.while.end:
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; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc
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bb.0.entry:
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successors: %bb.9(0x30000000), %bb.1(0x50000000)
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liveins: $r0, $r1, $r2, $r4, $r5, $r7, $lr
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frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
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frame-setup CFI_INSTRUCTION def_cfa_offset 16
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r7, -8
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frame-setup CFI_INSTRUCTION offset $r5, -12
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frame-setup CFI_INSTRUCTION offset $r4, -16
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tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr
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tBcc %bb.9, 0, killed $cpsr
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bb.1.while.body.preheader:
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successors: %bb.6(0x40000000), %bb.2(0x40000000)
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|
liveins: $r0, $r1, $r2
|
||
|
|
|
||
|
|
tCMPi8 renamable $r2, 4, 14, $noreg, implicit-def $cpsr
|
||
|
|
tBcc %bb.6, 3, killed $cpsr
|
||
|
|
|
||
|
|
bb.2.vector.memcheck:
|
||
|
|
successors: %bb.3(0x40000000), %bb.6(0x40000000)
|
||
|
|
liveins: $r0, $r1, $r2
|
||
|
|
|
||
|
|
renamable $r3 = t2ADDrs renamable $r0, renamable $r2, 18, 14, $noreg, $noreg
|
||
|
|
tCMPr killed renamable $r3, renamable $r1, 14, $noreg, implicit-def $cpsr
|
||
|
|
t2IT 8, 4, implicit-def $itstate
|
||
|
|
renamable $r3 = t2ADDrs renamable $r1, renamable $r2, 18, 8, $cpsr, $noreg, implicit $itstate
|
||
|
|
tCMPr killed renamable $r3, renamable $r0, 8, killed $cpsr, implicit-def $cpsr, implicit killed $itstate
|
||
|
|
tBcc %bb.6, 8, killed $cpsr
|
||
|
|
|
||
|
|
bb.3.vector.ph:
|
||
|
|
successors: %bb.4(0x80000000)
|
||
|
|
liveins: $r0, $r1, $r2
|
||
|
|
|
||
|
|
renamable $r4 = t2BICri renamable $r2, 3, 14, $noreg, $noreg
|
||
|
|
renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg
|
||
|
|
renamable $r12 = t2SUBri renamable $r4, 4, 14, $noreg, $noreg
|
||
|
|
renamable $r7, dead $cpsr = tSUBrr renamable $r2, renamable $r4, 14, $noreg
|
||
|
|
renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg
|
||
|
|
renamable $r12 = t2ADDrs renamable $r0, renamable $r4, 18, 14, $noreg, $noreg
|
||
|
|
$lr = t2DoLoopStart renamable $r3
|
||
|
|
renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 16, 14, $noreg
|
||
|
|
$r5 = tMOVr killed $r3, 14, $noreg
|
||
|
|
renamable $r3 = t2ADDrs renamable $r1, renamable $r4, 18, 14, $noreg, $noreg
|
||
|
|
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14, $noreg
|
||
|
|
|
||
|
|
bb.4.vector.body:
|
||
|
|
successors: %bb.4(0x7c000000), %bb.5(0x04000000)
|
||
|
|
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $r12
|
||
|
|
|
||
|
|
renamable $r0, renamable $q0 = MVE_VLDRWU32_pre killed renamable $r0, 16, 0, $noreg :: (load 16 from %ir.scevgep18, align 4)
|
||
|
|
$lr = tMOVr killed $r5, 14, $noreg
|
||
|
|
renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VABSf32 killed renamable $q0, 0, $noreg, undef renamable $q0
|
||
|
|
renamable $r1 = MVE_VSTRBU8_pre killed renamable $q0, killed renamable $r1, 16, 0, $noreg :: (store 16 into %ir.scevgep13, align 4)
|
||
|
|
renamable $lr = t2LoopDec killed renamable $lr, 1
|
||
|
|
$r5 = tMOVr $lr, 14, $noreg
|
||
|
|
t2LoopEnd killed renamable $lr, %bb.4, implicit-def dead $cpsr
|
||
|
|
tB %bb.5, 14, $noreg
|
||
|
|
|
||
|
|
bb.5.middle.block:
|
||
|
|
successors: %bb.7(0x80000000)
|
||
|
|
liveins: $r2, $r3, $r4, $r7, $r12
|
||
|
|
|
||
|
|
tCMPr killed renamable $r4, killed renamable $r2, 14, $noreg, implicit-def $cpsr
|
||
|
|
$lr = tMOVr killed $r7, 14, $noreg
|
||
|
|
t2IT 0, 8, implicit-def $itstate
|
||
|
|
tPOP_RET 0, killed $cpsr, def $r4, def $r5, def $r7, def $pc, implicit killed $itstate
|
||
|
|
tB %bb.7, 14, $noreg
|
||
|
|
|
||
|
|
bb.6:
|
||
|
|
successors: %bb.7(0x80000000)
|
||
|
|
liveins: $r0, $r1, $r2
|
||
|
|
|
||
|
|
$lr = tMOVr killed $r2, 14, $noreg
|
||
|
|
$r12 = tMOVr killed $r0, 14, $noreg
|
||
|
|
$r3 = tMOVr killed $r1, 14, $noreg
|
||
|
|
|
||
|
|
bb.7.while.body.preheader19:
|
||
|
|
successors: %bb.8(0x80000000)
|
||
|
|
liveins: $lr, $r3, $r12
|
||
|
|
|
||
|
|
renamable $r0, dead $cpsr = tSUBi3 killed renamable $r3, 4, 14, $noreg
|
||
|
|
renamable $r1 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
|
||
|
|
$lr = t2DoLoopStart renamable $lr
|
||
|
|
|
||
|
|
bb.8.while.body:
|
||
|
|
successors: %bb.8(0x7c000000), %bb.9(0x04000000)
|
||
|
|
liveins: $lr, $r0, $r1
|
||
|
|
|
||
|
|
renamable $s0 = VLDRS renamable $r1, 1, 14, $noreg :: (load 4 from %ir.scevgep3)
|
||
|
|
renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14, $noreg
|
||
|
|
renamable $s0 = nnan ninf nsz arcp contract afn reassoc VABSS killed renamable $s0, 14, $noreg
|
||
|
|
VSTRS killed renamable $s0, renamable $r0, 1, 14, $noreg :: (store 4 into %ir.scevgep7)
|
||
|
|
renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14, $noreg
|
||
|
|
renamable $lr = t2LoopDec killed renamable $lr, 1
|
||
|
|
t2LoopEnd renamable $lr, %bb.8, implicit-def dead $cpsr
|
||
|
|
tB %bb.9, 14, $noreg
|
||
|
|
|
||
|
|
bb.9.while.end:
|
||
|
|
tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc
|
||
|
|
|
||
|
|
...
|