169 lines
7.9 KiB
Plaintext
169 lines
7.9 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s
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--- |
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define dso_local arm_aapcs_vfpcc void @multi_cond_iter_count(i32* noalias nocapture %0, i32* nocapture readonly %1, i32 %2, i32 %3) {
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%5 = icmp eq i32 %3, 2
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%6 = select i1 %5, i32 2, i32 4
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%7 = icmp eq i32 %3, 4
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%8 = select i1 %7, i32 1, i32 %6
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%9 = shl i32 %2, %8
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%10 = icmp eq i32 %9, 0
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%11 = add i32 %9, 3
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%12 = lshr i32 %11, 2
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%13 = shl nuw i32 %12, 2
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%14 = add i32 %13, -4
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%15 = lshr i32 %14, 2
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%16 = add nuw nsw i32 %15, 1
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br i1 %10, label %34, label %17
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17: ; preds = %4
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%start = call i32 @llvm.start.loop.iterations.i32(i32 %16)
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br label %18
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18: ; preds = %18, %17
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%19 = phi i32* [ %31, %18 ], [ %0, %17 ]
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%20 = phi i32* [ %30, %18 ], [ %1, %17 ]
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%21 = phi i32 [ %start, %17 ], [ %32, %18 ]
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%22 = phi i32 [ %9, %17 ], [ %26, %18 ]
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%23 = bitcast i32* %19 to <4 x i32>*
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%24 = bitcast i32* %20 to <4 x i32>*
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%25 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %22)
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%26 = sub i32 %22, 4
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%27 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %24, i32 4, <4 x i1> %25, <4 x i32> undef)
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%28 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %23, i32 4, <4 x i1> %25, <4 x i32> undef)
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%29 = mul nsw <4 x i32> %28, %27
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call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %29, <4 x i32>* %23, i32 4, <4 x i1> %25)
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%30 = getelementptr i32, i32* %20, i32 4
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%31 = getelementptr i32, i32* %19, i32 4
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%32 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %21, i32 1)
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%33 = icmp ne i32 %32, 0
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br i1 %33, label %18, label %34
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34: ; preds = %18, %4
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ret void
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}
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declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>)
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declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>)
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declare i32 @llvm.start.loop.iterations.i32(i32)
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declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
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declare <4 x i1> @llvm.arm.mve.vctp32(i32)
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...
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---
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name: multi_cond_iter_count
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alignment: 2
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tracksRegLiveness: true
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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- { reg: '$r2', virtual-reg: '' }
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- { reg: '$r3', virtual-reg: '' }
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frameInfo:
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stackSize: 8
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offsetAdjustment: 0
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maxAlignment: 4
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fixedStack: []
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: multi_cond_iter_count
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; CHECK: bb.0 (%ir-block.4):
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
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; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
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; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
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; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
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; CHECK: tCMPi8 renamable $r3, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: $r12 = tMOVr $r3, 14 /* CC::al */, $noreg
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; CHECK: t2IT 1, 8, implicit-def $itstate
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; CHECK: $r12 = t2MOVi 4, 1 /* CC::ne */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
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; CHECK: tCMPi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: t2IT 0, 8, implicit-def $itstate
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; CHECK: $r12 = t2MOVi 1, 0 /* CC::eq */, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
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; CHECK: renamable $r2 = t2LSLrr killed renamable $r2, killed renamable $r12, 14 /* CC::al */, $noreg, def $cpsr
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; CHECK: t2IT 0, 8, implicit-def $itstate
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; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
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; CHECK: bb.1 (%ir-block.17):
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: liveins: $r0, $r1, $r2
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; CHECK: $r3 = tMOVr $r0, 14 /* CC::al */, $noreg
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; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
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; CHECK: bb.2 (%ir-block.18):
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; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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; CHECK: liveins: $lr, $r0, $r1, $r3
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; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg
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; CHECK: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 0, $noreg
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; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
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; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg
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; CHECK: $r0 = tMOVr $r3, 14 /* CC::al */, $noreg
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; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
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; CHECK: bb.3 (%ir-block.34):
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; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
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bb.0 (%ir-block.4):
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successors: %bb.1(0x80000000)
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liveins: $r0, $r1, $r2, $r3, $lr
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frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp
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frame-setup CFI_INSTRUCTION def_cfa_offset 8
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r7, -8
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$r7 = frame-setup tMOVr $sp, 14, $noreg
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frame-setup CFI_INSTRUCTION def_cfa_register $r7
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tCMPi8 renamable $r3, 2, 14, $noreg, implicit-def $cpsr
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$r12 = tMOVr $r3, 14, $noreg
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t2IT 1, 8, implicit-def $itstate
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$r12 = t2MOVi 4, 1, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
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tCMPi8 killed renamable $r3, 4, 14, $noreg, implicit-def $cpsr
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t2IT 0, 8, implicit-def $itstate
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$r12 = t2MOVi 1, 0, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate
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renamable $r2 = t2LSLrr killed renamable $r2, killed renamable $r12, 14, $noreg, def $cpsr
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t2IT 0, 8, implicit-def $itstate
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tPOP_RET 0, killed $cpsr, def $r7, def $pc, implicit killed $itstate
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bb.1 (%ir-block.17):
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successors: %bb.2(0x80000000)
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liveins: $r0, $r1, $r2, $r3, $lr
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renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg
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renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg
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renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg
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renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg
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renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg
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$r3 = tMOVr $r0, 14, $noreg
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$lr = t2DoLoopStart renamable $lr
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bb.2 (%ir-block.18):
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successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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liveins: $lr, $r0, $r1, $r2, $r3
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renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
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MVE_VPST 4, implicit $vpr
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renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr
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renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr
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renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
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renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
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MVE_VPST 8, implicit $vpr
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MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr
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renamable $lr = t2LoopDec killed renamable $lr, 1
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$r0 = tMOVr $r3, 14, $noreg
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t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
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tB %bb.3, 14, $noreg
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bb.3 (%ir-block.34):
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tPOP_RET 14, $noreg, def $r7, def $pc
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...
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