118 lines
4.7 KiB
Plaintext
118 lines
4.7 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s
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--- |
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@arr = external dso_local local_unnamed_addr global [0 x i32], align 4
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define dso_local arm_aapcs_vfpcc void @foo(i32 %i) {
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entry:
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%tobool.not11 = icmp eq i32 %i, 0
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br i1 %tobool.not11, label %for.end5, label %vector.ph.preheader
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vector.ph.preheader: ; preds = %entry
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%active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 0, i32 3)
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br label %vector.ph
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vector.ph: ; preds = %vector.ph.preheader, %vector.ph
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%i.addr.012 = phi i32 [ %math, %vector.ph ], [ %i, %vector.ph.preheader ]
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call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> <i32 2, i32 2, i32 2, i32 2>, <4 x i32>* bitcast ([0 x i32]* @arr to <4 x i32>*), i32 4, <4 x i1> %active.lane.mask)
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%0 = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %i.addr.012, i32 1)
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%math = extractvalue { i32, i1 } %0, 0
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%ov = extractvalue { i32, i1 } %0, 1
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br i1 %ov, label %for.end5, label %vector.ph
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for.end5: ; preds = %vector.ph, %entry
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ret void
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}
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declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
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declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>)
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declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32)
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...
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---
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name: foo
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alignment: 8
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tracksRegLiveness: true
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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frameInfo:
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maxAlignment: 1
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack: []
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callSites: []
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constants:
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- id: 0
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value: '<4 x i32> <i32 0, i32 1, i32 2, i32 3>'
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alignment: 8
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isTargetSpecific: false
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: foo
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; CHECK: bb.0.entry:
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; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000)
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; CHECK: liveins: $r0
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; CHECK: tCBZ $r0, %bb.3
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; CHECK: bb.1.vector.ph.preheader:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: liveins: $r0
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; CHECK: renamable $r1 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
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; CHECK: renamable $q0 = MVE_VMOVimmi32 3, 0, $noreg, undef renamable $q0
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; CHECK: renamable $q1 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg :: (load 16 from constant-pool, align 8)
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; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @arr, 14 /* CC::al */, $noreg
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; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @arr, 14 /* CC::al */, $noreg
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; CHECK: renamable $vpr = MVE_VCMPu32 killed renamable $q0, killed renamable $q1, 8, 0, $noreg
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; CHECK: renamable $q0 = MVE_VMOVimmi32 2, 0, $noreg, undef renamable $q0
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; CHECK: bb.2.vector.ph:
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; CHECK: successors: %bb.3(0x04000000), %bb.2(0x7c000000)
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; CHECK: liveins: $vpr, $q0, $r0, $r1
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; CHECK: renamable $r0, $cpsr = tADDi8 killed renamable $r0, 1, 14 /* CC::al */, $noreg
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; CHECK: MVE_VPST 8, implicit $vpr
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; CHECK: MVE_VSTRWU32 renamable $q0, renamable $r1, 0, 1, renamable $vpr :: (store 16 into `<4 x i32>* bitcast ([0 x i32]* @arr to <4 x i32>*)`, align 4)
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; CHECK: tBcc %bb.2, 3 /* CC::lo */, killed $cpsr
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; CHECK: bb.3.for.end5:
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; CHECK: tBX_RET 14 /* CC::al */, $noreg
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; CHECK: bb.4 (align 8):
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; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16
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bb.0.entry:
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successors: %bb.3(0x30000000), %bb.1(0x50000000)
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liveins: $r0
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tCBZ $r0, %bb.3
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bb.1.vector.ph.preheader:
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successors: %bb.2(0x80000000)
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liveins: $r0
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renamable $r1 = tLEApcrel %const.0, 14 /* CC::al */, $noreg
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renamable $q0 = MVE_VMOVimmi32 3, 0, $noreg, undef renamable $q0
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renamable $q1 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg :: (load 16 from constant-pool, align 8)
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$r1 = t2MOVi16 target-flags(arm-lo16) @arr, 14 /* CC::al */, $noreg
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$r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @arr, 14 /* CC::al */, $noreg
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renamable $vpr = MVE_VCMPu32 killed renamable $q0, killed renamable $q1, 8, 0, $noreg
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renamable $q0 = MVE_VMOVimmi32 2, 0, $noreg, undef renamable $q0
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bb.2.vector.ph:
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successors: %bb.3(0x04000000), %bb.2(0x7c000000)
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liveins: $vpr, $q0, $r0, $r1
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renamable $r0, $cpsr = tADDi8 killed renamable $r0, 1, 14 /* CC::al */, $noreg
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MVE_VPST 8, implicit $vpr
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MVE_VSTRWU32 renamable $q0, renamable $r1, 0, 1, renamable $vpr :: (store 16 into `<4 x i32>* bitcast ([0 x i32]* @arr to <4 x i32>*)`, align 4)
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tBcc %bb.2, 3 /* CC::lo */, killed $cpsr
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bb.3.for.end5:
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tBX_RET 14 /* CC::al */, $noreg
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bb.4 (align 8):
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CONSTPOOL_ENTRY 0, %const.0, 16
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...
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