25 lines
807 B
LLVM
25 lines
807 B
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
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; RUN: --riscv-no-aliases < %s | FileCheck %s
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declare <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8(
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<vscale x 1 x i8>,
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i8,
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i32);
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define <vscale x 1 x i8> @intrinsic_vslide1up_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
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; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i8_nxv1i8_i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
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; CHECK-NEXT: vslide1up.vx v25, v8, a0
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; CHECK-NEXT: vmv1r.v v8, v25
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; CHECK-NEXT: jalr zero, 0(ra)
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entry:
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%a = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8(
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<vscale x 1 x i8> %0,
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i8 %1,
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i32 %2)
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ret <vscale x 1 x i8> %a
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}
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