llvm-for-llvmta/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll

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2022-04-25 10:02:23 +02:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple riscv64 -mattr=+m,+experimental-v < %s \
; RUN: | FileCheck %s
define i64 @vscale_zero() nounwind {
; CHECK-LABEL: vscale_zero:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mv a0, zero
; CHECK-NEXT: ret
entry:
%0 = call i64 @llvm.vscale.i64()
%1 = mul i64 %0, 0
ret i64 %1
}
define i64 @vscale_one() nounwind {
; CHECK-LABEL: vscale_one:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: ret
entry:
%0 = call i64 @llvm.vscale.i64()
%1 = mul i64 %0, 1
ret i64 %1
}
define i64 @vscale_uimmpow2xlen() nounwind {
; CHECK-LABEL: vscale_uimmpow2xlen:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: ret
entry:
%0 = call i64 @llvm.vscale.i64()
%1 = mul i64 %0, 64
ret i64 %1
}
define i64 @vscale_non_pow2() nounwind {
; CHECK-LABEL: vscale_non_pow2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a1, zero, 24
; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: ret
entry:
%0 = call i64 @llvm.vscale.i64()
%1 = mul i64 %0, 24
ret i64 %1
}
declare i64 @llvm.vscale.i64()