142 lines
3.7 KiB
LLVM
142 lines
3.7 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s
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target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32"
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define void @foo1(i16* %p, i16* %r) nounwind {
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; CHECK-LABEL: foo1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lhz 3, 0(3)
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; CHECK-NEXT: sth 3, 0(4)
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; CHECK-NEXT: blr
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;
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; CHECK-VSX-LABEL: foo1:
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; CHECK-VSX: # %bb.0: # %entry
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; CHECK-VSX-NEXT: lhz 3, 0(3)
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; CHECK-VSX-NEXT: sth 3, 0(4)
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; CHECK-VSX-NEXT: blr
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entry:
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%v = load i16, i16* %p, align 1
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store i16 %v, i16* %r, align 1
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ret void
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}
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define void @foo2(i32* %p, i32* %r) nounwind {
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; CHECK-LABEL: foo2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lwz 3, 0(3)
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; CHECK-NEXT: stw 3, 0(4)
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; CHECK-NEXT: blr
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;
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; CHECK-VSX-LABEL: foo2:
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; CHECK-VSX: # %bb.0: # %entry
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; CHECK-VSX-NEXT: lwz 3, 0(3)
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; CHECK-VSX-NEXT: stw 3, 0(4)
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; CHECK-VSX-NEXT: blr
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entry:
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%v = load i32, i32* %p, align 1
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store i32 %v, i32* %r, align 1
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ret void
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}
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define void @foo3(i64* %p, i64* %r) nounwind {
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; CHECK-LABEL: foo3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: ld 3, 0(3)
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; CHECK-NEXT: std 3, 0(4)
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; CHECK-NEXT: blr
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;
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; CHECK-VSX-LABEL: foo3:
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; CHECK-VSX: # %bb.0: # %entry
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; CHECK-VSX-NEXT: ld 3, 0(3)
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; CHECK-VSX-NEXT: std 3, 0(4)
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; CHECK-VSX-NEXT: blr
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entry:
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%v = load i64, i64* %p, align 1
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store i64 %v, i64* %r, align 1
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ret void
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}
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define void @foo4(float* %p, float* %r) nounwind {
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; CHECK-LABEL: foo4:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lfs 0, 0(3)
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; CHECK-NEXT: stfs 0, 0(4)
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; CHECK-NEXT: blr
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;
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; CHECK-VSX-LABEL: foo4:
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; CHECK-VSX: # %bb.0: # %entry
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; CHECK-VSX-NEXT: lfs 0, 0(3)
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; CHECK-VSX-NEXT: stfs 0, 0(4)
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; CHECK-VSX-NEXT: blr
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entry:
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%v = load float, float* %p, align 1
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store float %v, float* %r, align 1
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ret void
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}
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define void @foo5(double* %p, double* %r) nounwind {
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; CHECK-LABEL: foo5:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lfd 0, 0(3)
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; CHECK-NEXT: stfd 0, 0(4)
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; CHECK-NEXT: blr
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;
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; CHECK-VSX-LABEL: foo5:
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; CHECK-VSX: # %bb.0: # %entry
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; CHECK-VSX-NEXT: lfdx 0, 0, 3
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; CHECK-VSX-NEXT: stfdx 0, 0, 4
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; CHECK-VSX-NEXT: blr
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entry:
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%v = load double, double* %p, align 1
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store double %v, double* %r, align 1
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ret void
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}
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define void @foo6(<4 x float>* %p, <4 x float>* %r) nounwind {
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; These loads and stores are legalized into aligned loads and stores
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; using aligned stack slots.
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; CHECK-LABEL: foo6:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 5, 15
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; CHECK-NEXT: lvsl 3, 0, 3
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; CHECK-NEXT: lvx 2, 3, 5
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; CHECK-NEXT: lvx 4, 0, 3
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; CHECK-NEXT: addi 3, 1, -16
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; CHECK-NEXT: vperm 2, 4, 2, 3
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; CHECK-NEXT: stvx 2, 0, 3
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; CHECK-NEXT: ld 3, -8(1)
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; CHECK-NEXT: std 3, 8(4)
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; CHECK-NEXT: ld 3, -16(1)
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; CHECK-NEXT: std 3, 0(4)
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; CHECK-NEXT: blr
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;
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; CHECK-VSX-LABEL: foo6:
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; CHECK-VSX: # %bb.0: # %entry
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; CHECK-VSX-NEXT: li 5, 15
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; CHECK-VSX-NEXT: lvsl 3, 0, 3
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; CHECK-VSX-NEXT: lvx 2, 3, 5
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; CHECK-VSX-NEXT: lvx 4, 0, 3
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; CHECK-VSX-NEXT: vperm 2, 4, 2, 3
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; CHECK-VSX-NEXT: stxvw4x 34, 0, 4
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; CHECK-VSX-NEXT: blr
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; For VSX on P7, unaligned loads and stores are preferable to aligned
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; stack slots, but lvsl/vperm is better still. (On P8 lxvw4x is preferable.)
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; Using unaligned stxvw4x is preferable on both machines.
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entry:
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%v = load <4 x float>, <4 x float>* %p, align 1
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store <4 x float> %v, <4 x float>* %r, align 1
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ret void
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}
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