llvm-for-llvmta/test/CodeGen/PowerPC/sms-phi-5.ll

57 lines
1.6 KiB
LLVM
Raw Permalink Normal View History

2022-04-25 10:02:23 +02:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\
; RUN: -mcpu=pwr9 --ppc-enable-pipeliner 2>&1 | FileCheck %s
define void @phi5() unnamed_addr {
; CHECK-LABEL: phi5:
; CHECK: # %bb.0:
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li 3, 0
; CHECK-NEXT: li 4, 1
; CHECK-NEXT: slw 3, 4, 3
; CHECK-NEXT: andi. 3, 3, 6336
; CHECK-NEXT: beqlr 0
; CHECK-NEXT: # %bb.2:
; CHECK-NEXT: lhz 3, 0(3)
; CHECK-NEXT: slwi 3, 3, 15
; CHECK-NEXT: clrlwi 3, 3, 31
; CHECK-NEXT: rlwinm 4, 3, 31, 17, 31
; CHECK-NEXT: or 3, 3, 4
; CHECK-NEXT: rlwimi 3, 3, 15, 0, 16
; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: blr
switch i12 undef, label %21 [
i12 6, label %1
i12 7, label %1
i12 12, label %1
i12 11, label %1
]
1: ; preds = %0, %0, %0, %0
%2 = load i16, i16* undef, align 2
br label %3
3: ; preds = %3, %1
%4 = phi i16 [ %18, %3 ], [ undef, %1 ]
%5 = phi i16 [ %13, %3 ], [ undef, %1 ]
%6 = phi i16 [ %11, %3 ], [ undef, %1 ]
%7 = phi i16 [ undef, %3 ], [ %2, %1 ]
%8 = phi i32 [ %19, %3 ], [ undef, %1 ]
%9 = lshr i16 %6, 1
%10 = shl i16 %7, 15
%11 = or i16 %10, %9
%12 = shl i16 %6, 15
%13 = or i16 %12, 0
%14 = and i16 %4, 1
%15 = lshr i16 %4, 1
%16 = shl i16 %5, 15
%17 = or i16 %14, %15
%18 = or i16 %17, %16
%19 = add i32 %8, -1
%20 = icmp eq i32 %19, 0
br i1 %20, label %21, label %3
21: ; preds = %3, %0
ret void
}