316 lines
8.2 KiB
LLVM
316 lines
8.2 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
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; RUN: -mtriple=powerpc64le-linux-gnu < %s | FileCheck \
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; RUN: -check-prefix=CHECK-LE %s
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; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
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; RUN: -mtriple=powerpc-linux-gnu < %s | FileCheck \
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; RUN: -check-prefix=CHECK-32 %s
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define i64 @f0(i64 %x) {
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; CHECK-LE-LABEL: f0:
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; CHECK-LE: # %bb.0:
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; CHECK-LE-NEXT: li r4, 125
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; CHECK-LE-NEXT: cmpdi r3, 0
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; CHECK-LE-NEXT: li r3, -3
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; CHECK-LE-NEXT: isellt r3, r3, r4
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; CHECK-LE-NEXT: blr
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;
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; CHECK-32-LABEL: f0:
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; CHECK-32: # %bb.0:
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; CHECK-32-NEXT: li r4, 125
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; CHECK-32-NEXT: li r5, -3
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; CHECK-32-NEXT: cmpwi r3, 0
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; CHECK-32-NEXT: bc 12, lt, .LBB0_1
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; CHECK-32-NEXT: b .LBB0_2
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; CHECK-32-NEXT: .LBB0_1:
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; CHECK-32-NEXT: addi r4, r5, 0
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; CHECK-32-NEXT: .LBB0_2:
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; CHECK-32-NEXT: srawi r3, r3, 31
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; CHECK-32-NEXT: blr
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%c = icmp slt i64 %x, 0
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%r = select i1 %c, i64 -3, i64 125
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ret i64 %r
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}
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define i64 @f1(i64 %x) {
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; CHECK-LE-LABEL: f1:
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; CHECK-LE: # %bb.0:
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; CHECK-LE-NEXT: li r4, 512
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; CHECK-LE-NEXT: cmpdi r3, 0
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; CHECK-LE-NEXT: li r3, 64
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; CHECK-LE-NEXT: isellt r3, r3, r4
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; CHECK-LE-NEXT: blr
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;
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; CHECK-32-LABEL: f1:
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; CHECK-32: # %bb.0:
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; CHECK-32-NEXT: li r4, 512
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; CHECK-32-NEXT: cmpwi r3, 0
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; CHECK-32-NEXT: li r3, 64
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; CHECK-32-NEXT: bc 12, lt, .LBB1_1
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; CHECK-32-NEXT: b .LBB1_2
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; CHECK-32-NEXT: .LBB1_1:
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; CHECK-32-NEXT: addi r4, r3, 0
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; CHECK-32-NEXT: .LBB1_2:
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; CHECK-32-NEXT: li r3, 0
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; CHECK-32-NEXT: blr
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%c = icmp slt i64 %x, 0
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%r = select i1 %c, i64 64, i64 512
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ret i64 %r
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}
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define i64 @f2(i64 %x) {
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; CHECK-LE-LABEL: f2:
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; CHECK-LE: # %bb.0:
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; CHECK-LE-NEXT: li r4, 1024
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; CHECK-LE-NEXT: cmpdi r3, 0
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; CHECK-LE-NEXT: iseleq r3, 0, r4
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; CHECK-LE-NEXT: blr
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;
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; CHECK-32-LABEL: f2:
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; CHECK-32: # %bb.0:
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; CHECK-32-NEXT: or. r3, r4, r3
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; CHECK-32-NEXT: li r3, 1024
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; CHECK-32-NEXT: bc 12, eq, .LBB2_2
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; CHECK-32-NEXT: # %bb.1:
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; CHECK-32-NEXT: ori r4, r3, 0
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; CHECK-32-NEXT: b .LBB2_3
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; CHECK-32-NEXT: .LBB2_2:
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; CHECK-32-NEXT: li r4, 0
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; CHECK-32-NEXT: .LBB2_3:
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; CHECK-32-NEXT: li r3, 0
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; CHECK-32-NEXT: blr
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%c = icmp eq i64 %x, 0
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%r = select i1 %c, i64 0, i64 1024
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ret i64 %r
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}
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define i64 @f3(i64 %x, i64 %y) {
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; CHECK-LE-LABEL: f3:
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; CHECK-LE: # %bb.0:
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; CHECK-LE-NEXT: cmpldi r3, 0
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; CHECK-LE-NEXT: iseleq r3, 0, r4
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; CHECK-LE-NEXT: blr
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;
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; CHECK-32-LABEL: f3:
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; CHECK-32: # %bb.0:
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; CHECK-32-NEXT: or. r3, r4, r3
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; CHECK-32-NEXT: bc 12, eq, .LBB3_2
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; CHECK-32-NEXT: # %bb.1:
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; CHECK-32-NEXT: ori r3, r5, 0
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; CHECK-32-NEXT: ori r4, r6, 0
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; CHECK-32-NEXT: blr
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; CHECK-32-NEXT: .LBB3_2:
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; CHECK-32-NEXT: li r3, 0
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; CHECK-32-NEXT: li r4, 0
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; CHECK-32-NEXT: blr
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%c = icmp eq i64 %x, 0
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%r = select i1 %c, i64 0, i64 %y
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ret i64 %r
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}
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define i64 @f4(i64 %x) {
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; CHECK-LE-LABEL: f4:
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; CHECK-LE: # %bb.0:
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; CHECK-LE-NEXT: sradi r4, r3, 63
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; CHECK-LE-NEXT: xor r3, r3, r4
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; CHECK-LE-NEXT: sub r3, r4, r3
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; CHECK-LE-NEXT: blr
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;
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; CHECK-32-LABEL: f4:
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; CHECK-32: # %bb.0:
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; CHECK-32-NEXT: srawi r5, r3, 31
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; CHECK-32-NEXT: xor r4, r4, r5
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; CHECK-32-NEXT: xor r3, r3, r5
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; CHECK-32-NEXT: subc r4, r5, r4
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; CHECK-32-NEXT: subfe r3, r3, r5
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; CHECK-32-NEXT: blr
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%c = icmp sgt i64 %x, 0
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%x.neg = sub i64 0, %x
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%r = select i1 %c, i64 %x.neg, i64 %x
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ret i64 %r
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}
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define i64 @f4_sge_0(i64 %x) {
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; CHECK-LE-LABEL: f4_sge_0:
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; CHECK-LE: # %bb.0:
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; CHECK-LE-NEXT: neg r4, r3
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; CHECK-LE-NEXT: cmpdi r3, -1
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; CHECK-LE-NEXT: iselgt r3, r4, r3
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; CHECK-LE-NEXT: blr
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;
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; CHECK-32-LABEL: f4_sge_0:
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; CHECK-32: # %bb.0:
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; CHECK-32-NEXT: subfic r5, r4, 0
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; CHECK-32-NEXT: subfze r6, r3
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; CHECK-32-NEXT: cmpwi r3, -1
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; CHECK-32-NEXT: bc 12, gt, .LBB5_1
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; CHECK-32-NEXT: blr
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; CHECK-32-NEXT: .LBB5_1:
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; CHECK-32-NEXT: addi r3, r6, 0
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; CHECK-32-NEXT: addi r4, r5, 0
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; CHECK-32-NEXT: blr
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%c = icmp sge i64 %x, 0
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%x.neg = sub i64 0, %x
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%r = select i1 %c, i64 %x.neg, i64 %x
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ret i64 %r
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}
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define i64 @f4_slt_0(i64 %x) {
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; CHECK-LE-LABEL: f4_slt_0:
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; CHECK-LE: # %bb.0:
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; CHECK-LE-NEXT: sradi r4, r3, 63
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; CHECK-LE-NEXT: xor r3, r3, r4
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; CHECK-LE-NEXT: sub r3, r4, r3
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; CHECK-LE-NEXT: blr
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;
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; CHECK-32-LABEL: f4_slt_0:
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; CHECK-32: # %bb.0:
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; CHECK-32-NEXT: srawi r5, r3, 31
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; CHECK-32-NEXT: xor r4, r4, r5
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; CHECK-32-NEXT: xor r3, r3, r5
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; CHECK-32-NEXT: subc r4, r5, r4
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; CHECK-32-NEXT: subfe r3, r3, r5
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; CHECK-32-NEXT: blr
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%c = icmp slt i64 %x, 0
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%x.neg = sub i64 0, %x
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%r = select i1 %c, i64 %x, i64 %x.neg
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ret i64 %r
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}
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define i64 @f4_sle_0(i64 %x) {
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; CHECK-LE-LABEL: f4_sle_0:
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; CHECK-LE: # %bb.0:
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; CHECK-LE-NEXT: neg r4, r3
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; CHECK-LE-NEXT: cmpdi r3, 1
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; CHECK-LE-NEXT: isellt r3, r3, r4
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; CHECK-LE-NEXT: blr
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;
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; CHECK-32-LABEL: f4_sle_0:
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; CHECK-32: # %bb.0:
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; CHECK-32-NEXT: cmplwi r3, 0
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; CHECK-32-NEXT: cmpwi cr1, r3, 0
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; CHECK-32-NEXT: crandc 4*cr5+lt, 4*cr1+lt, eq
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; CHECK-32-NEXT: cmpwi cr1, r4, 0
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; CHECK-32-NEXT: subfic r5, r4, 0
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; CHECK-32-NEXT: crand 4*cr5+gt, eq, 4*cr1+eq
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; CHECK-32-NEXT: cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
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; CHECK-32-NEXT: subfze r6, r3
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; CHECK-32-NEXT: bclr 12, 4*cr5+lt, 0
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; CHECK-32-NEXT: # %bb.1:
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; CHECK-32-NEXT: ori r3, r6, 0
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; CHECK-32-NEXT: ori r4, r5, 0
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; CHECK-32-NEXT: blr
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%c = icmp sle i64 %x, 0
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%x.neg = sub i64 0, %x
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%r = select i1 %c, i64 %x, i64 %x.neg
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ret i64 %r
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}
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define i64 @f4_sgt_m1(i64 %x) {
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; CHECK-LE-LABEL: f4_sgt_m1:
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; CHECK-LE: # %bb.0:
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; CHECK-LE-NEXT: sradi r4, r3, 63
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; CHECK-LE-NEXT: xor r3, r3, r4
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; CHECK-LE-NEXT: sub r3, r4, r3
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; CHECK-LE-NEXT: blr
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;
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; CHECK-32-LABEL: f4_sgt_m1:
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; CHECK-32: # %bb.0:
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; CHECK-32-NEXT: srawi r5, r3, 31
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; CHECK-32-NEXT: xor r4, r4, r5
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; CHECK-32-NEXT: xor r3, r3, r5
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; CHECK-32-NEXT: subc r4, r5, r4
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; CHECK-32-NEXT: subfe r3, r3, r5
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; CHECK-32-NEXT: blr
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%c = icmp sgt i64 %x, -1
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%x.neg = sub i64 0, %x
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%r = select i1 %c, i64 %x.neg, i64 %x
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ret i64 %r
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}
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define i64 @f5(i64 %x, i64 %y) {
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; CHECK-LE-LABEL: f5:
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; CHECK-LE: # %bb.0:
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; CHECK-LE-NEXT: li r5, 0
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; CHECK-LE-NEXT: cmpldi r3, 0
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; CHECK-LE-NEXT: iseleq r3, r4, r5
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; CHECK-LE-NEXT: blr
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;
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; CHECK-32-LABEL: f5:
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; CHECK-32: # %bb.0:
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; CHECK-32-NEXT: li r7, 0
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; CHECK-32-NEXT: or. r3, r4, r3
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; CHECK-32-NEXT: bc 12, eq, .LBB9_2
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; CHECK-32-NEXT: # %bb.1:
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; CHECK-32-NEXT: ori r3, r7, 0
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; CHECK-32-NEXT: ori r4, r7, 0
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; CHECK-32-NEXT: blr
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; CHECK-32-NEXT: .LBB9_2:
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; CHECK-32-NEXT: addi r3, r5, 0
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; CHECK-32-NEXT: addi r4, r6, 0
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; CHECK-32-NEXT: blr
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%c = icmp eq i64 %x, 0
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%r = select i1 %c, i64 %y, i64 0
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ret i64 %r
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}
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define i32 @f5_i32(i32 %x, i32 %y) {
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; CHECK-LE-LABEL: f5_i32:
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; CHECK-LE: # %bb.0:
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; CHECK-LE-NEXT: li r5, 0
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; CHECK-LE-NEXT: cmplwi r3, 0
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; CHECK-LE-NEXT: iseleq r3, r4, r5
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; CHECK-LE-NEXT: blr
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;
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; CHECK-32-LABEL: f5_i32:
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; CHECK-32: # %bb.0:
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; CHECK-32-NEXT: li r5, 0
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; CHECK-32-NEXT: cmplwi r3, 0
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; CHECK-32-NEXT: bc 12, eq, .LBB10_2
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; CHECK-32-NEXT: # %bb.1:
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; CHECK-32-NEXT: ori r3, r5, 0
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; CHECK-32-NEXT: blr
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; CHECK-32-NEXT: .LBB10_2:
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; CHECK-32-NEXT: addi r3, r4, 0
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; CHECK-32-NEXT: blr
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%c = icmp eq i32 %x, 0
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%r = select i1 %c, i32 %y, i32 0
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ret i32 %r
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}
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define i64 @f6(i64 %x) {
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; CHECK-LE-LABEL: f6:
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; CHECK-LE: # %bb.0:
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; CHECK-LE-NEXT: cntlzd r3, r3
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; CHECK-LE-NEXT: rldicl r3, r3, 58, 63
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; CHECK-LE-NEXT: blr
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;
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; CHECK-32-LABEL: f6:
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; CHECK-32: # %bb.0:
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; CHECK-32-NEXT: or r3, r4, r3
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; CHECK-32-NEXT: cntlzw r3, r3
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; CHECK-32-NEXT: rlwinm r4, r3, 27, 31, 31
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; CHECK-32-NEXT: li r3, 0
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; CHECK-32-NEXT: blr
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%c = icmp ne i64 %x, 0
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%r = select i1 %c, i64 0, i64 1
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ret i64 %r
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}
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define i32 @f6_i32(i32 %x) {
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; CHECK-LE-LABEL: f6_i32:
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; CHECK-LE: # %bb.0:
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; CHECK-LE-NEXT: cntlzw r3, r3
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; CHECK-LE-NEXT: srwi r3, r3, 5
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; CHECK-LE-NEXT: blr
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;
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; CHECK-32-LABEL: f6_i32:
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; CHECK-32: # %bb.0:
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; CHECK-32-NEXT: cntlzw r3, r3
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; CHECK-32-NEXT: rlwinm r3, r3, 27, 31, 31
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; CHECK-32-NEXT: blr
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%c = icmp ne i32 %x, 0
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%r = select i1 %c, i32 0, i32 1
|
||
|
|
ret i32 %r
|
||
|
|
}
|