62 lines
2.2 KiB
LLVM
62 lines
2.2 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -enable-mssa-loop-dependency=false -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown < %s | \
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; RUN: FileCheck %s
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; RUN: llc -enable-mssa-loop-dependency=true -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown < %s | \
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; RUN: FileCheck %s --check-prefix=MSSA
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; Function Attrs: nounwind
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define void @ec_GFp_nistp256_points_mul() {
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; CHECK-LABEL: ec_GFp_nistp256_points_mul:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: ld 5, 0(3)
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; CHECK-NEXT: li 3, 127
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; CHECK-NEXT: li 4, 0
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; CHECK-NEXT: .p2align 5
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; CHECK-NEXT: .LBB0_1: # %fe_cmovznz.exit.i534.i.15
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; CHECK-NEXT: #
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; CHECK-NEXT: subfic 6, 5, 0
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; CHECK-NEXT: subfze 6, 4
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; CHECK-NEXT: sradi 7, 6, 63
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; CHECK-NEXT: srad 6, 6, 3
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; CHECK-NEXT: subc 5, 7, 5
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; CHECK-NEXT: subfe 5, 4, 6
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; CHECK-NEXT: sradi 5, 5, 63
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; CHECK-NEXT: b .LBB0_1
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;
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; MSSA-LABEL: ec_GFp_nistp256_points_mul:
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; MSSA: # %bb.0: # %entry
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; MSSA-NEXT: ld 3, 0(3)
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; MSSA-NEXT: li 4, 0
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; MSSA-NEXT: subfic 5, 3, 0
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; MSSA-NEXT: subfze 5, 4
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; MSSA-NEXT: sradi 5, 5, 63
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; MSSA-NEXT: subc 3, 5, 3
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; MSSA-NEXT: subfe 3, 4, 5
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; MSSA-NEXT: sradi 3, 3, 63
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; MSSA-NEXT: std 3, 0(3)
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; MSSA-NEXT: .p2align 4
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; MSSA-NEXT: .LBB0_1: # %fe_cmovznz.exit.i534.i.15
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; MSSA-NEXT: #
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; MSSA-NEXT: b .LBB0_1
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; With MemorySSA, everything is taken out of the loop by licm.
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; Loads and stores to undef are treated as non-aliasing.
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entry:
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br label %fe_cmovznz.exit.i534.i.15
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fe_cmovznz.exit.i534.i.15: ; preds = %fe_cmovznz.exit.i534.i.15, %entry
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%0 = load i64, i64* undef, align 8
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%1 = load i64, i64* undef, align 8
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%conv.i69.i.i = zext i64 %0 to i128
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%sub.i72.i.i = sub nsw i128 0, %conv.i69.i.i
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%conv.i63.i.i = zext i64 %1 to i128
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%add.neg.i.i.i = ashr i128 %sub.i72.i.i, 127
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%sub.i65.i.i = sub nsw i128 %add.neg.i.i.i, %conv.i63.i.i
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%sub.i65.lobit.i.i = ashr i128 %sub.i65.i.i, 127
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%conv1.i58.i.i = and i128 %sub.i65.lobit.i.i, 18446744073709551615
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%add3.i59.i.i = add nuw nsw i128 %conv1.i58.i.i, 0
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%conv4.i60.i.i = trunc i128 %add3.i59.i.i to i64
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store i64 %conv4.i60.i.i, i64* undef, align 16
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br label %fe_cmovznz.exit.i534.i.15
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}
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