358 lines
12 KiB
LLVM
358 lines
12 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O3 \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O3 \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mattr=-mma \
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; RUN: < %s | FileCheck %s --check-prefix=CHECK-NOMMA
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O3 \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: < %s | FileCheck %s --check-prefix=CHECK-BE
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O3 \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mattr=-mma \
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; RUN: < %s | FileCheck %s --check-prefix=CHECK-BE-NOMMA
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; This test also checks that the paired vector intrinsics are available even
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; when MMA is disabled.
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; assemble_pair
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declare <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8>, <16 x i8>)
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define void @ass_pair(<256 x i1>* %ptr, <16 x i8> %vc) {
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; CHECK-LABEL: ass_pair:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmr v3, v2
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; CHECK-NEXT: stxv v2, 16(r3)
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; CHECK-NEXT: stxv v3, 0(r3)
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; CHECK-NEXT: blr
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;
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; CHECK-NOMMA-LABEL: ass_pair:
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; CHECK-NOMMA: # %bb.0: # %entry
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; CHECK-NOMMA-NEXT: vmr v3, v2
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; CHECK-NOMMA-NEXT: stxv v2, 16(r3)
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; CHECK-NOMMA-NEXT: stxv v3, 0(r3)
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; CHECK-NOMMA-NEXT: blr
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;
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; CHECK-BE-LABEL: ass_pair:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: vmr v3, v2
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; CHECK-BE-NEXT: stxv v2, 16(r3)
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; CHECK-BE-NEXT: stxv v2, 0(r3)
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; CHECK-BE-NEXT: blr
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;
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; CHECK-BE-NOMMA-LABEL: ass_pair:
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; CHECK-BE-NOMMA: # %bb.0: # %entry
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; CHECK-BE-NOMMA-NEXT: vmr v3, v2
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; CHECK-BE-NOMMA-NEXT: stxv v2, 16(r3)
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; CHECK-BE-NOMMA-NEXT: stxv v2, 0(r3)
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; CHECK-BE-NOMMA-NEXT: blr
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entry:
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%0 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc, <16 x i8> %vc)
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store <256 x i1> %0, <256 x i1>* %ptr, align 32
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ret void
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}
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; disassemble_pair
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declare { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1>)
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define void @disass_pair(<256 x i1>* %ptr1, <16 x i8>* %ptr2, <16 x i8>* %ptr3) {
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; CHECK-LABEL: disass_pair:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxv vs1, 0(r3)
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; CHECK-NEXT: lxv vs0, 16(r3)
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; CHECK-NEXT: stxv vs1, 0(r4)
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; CHECK-NEXT: stxv vs0, 0(r5)
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; CHECK-NEXT: blr
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;
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; CHECK-NOMMA-LABEL: disass_pair:
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; CHECK-NOMMA: # %bb.0: # %entry
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; CHECK-NOMMA-NEXT: lxv vs1, 0(r3)
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; CHECK-NOMMA-NEXT: lxv vs0, 16(r3)
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; CHECK-NOMMA-NEXT: stxv vs1, 0(r4)
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; CHECK-NOMMA-NEXT: stxv vs0, 0(r5)
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; CHECK-NOMMA-NEXT: blr
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;
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; CHECK-BE-LABEL: disass_pair:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: lxv vs1, 16(r3)
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; CHECK-BE-NEXT: lxv vs0, 0(r3)
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; CHECK-BE-NEXT: stxv vs0, 0(r4)
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; CHECK-BE-NEXT: stxv vs1, 0(r5)
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; CHECK-BE-NEXT: blr
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;
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; CHECK-BE-NOMMA-LABEL: disass_pair:
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; CHECK-BE-NOMMA: # %bb.0: # %entry
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; CHECK-BE-NOMMA-NEXT: lxv vs1, 16(r3)
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; CHECK-BE-NOMMA-NEXT: lxv vs0, 0(r3)
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; CHECK-BE-NOMMA-NEXT: stxv vs0, 0(r4)
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; CHECK-BE-NOMMA-NEXT: stxv vs1, 0(r5)
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; CHECK-BE-NOMMA-NEXT: blr
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entry:
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%0 = load <256 x i1>, <256 x i1>* %ptr1, align 32
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%1 = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> %0)
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%2 = extractvalue { <16 x i8>, <16 x i8> } %1, 0
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%3 = extractvalue { <16 x i8>, <16 x i8> } %1, 1
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store <16 x i8> %2, <16 x i8>* %ptr2, align 16
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store <16 x i8> %3, <16 x i8>* %ptr3, align 16
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ret void
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}
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define void @test_ldst_1(<256 x i1>* %vpp, <256 x i1>* %vp2) {
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; CHECK-LABEL: test_ldst_1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxvp vsp0, 0(r3)
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; CHECK-NEXT: stxvp vsp0, 0(r4)
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; CHECK-NEXT: blr
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;
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; CHECK-NOMMA-LABEL: test_ldst_1:
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; CHECK-NOMMA: # %bb.0: # %entry
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; CHECK-NOMMA-NEXT: lxvp vsp0, 0(r3)
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; CHECK-NOMMA-NEXT: stxvp vsp0, 0(r4)
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; CHECK-NOMMA-NEXT: blr
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;
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; CHECK-BE-LABEL: test_ldst_1:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: lxvp vsp0, 0(r3)
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; CHECK-BE-NEXT: stxvp vsp0, 0(r4)
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; CHECK-BE-NEXT: blr
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;
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; CHECK-BE-NOMMA-LABEL: test_ldst_1:
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; CHECK-BE-NOMMA: # %bb.0: # %entry
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; CHECK-BE-NOMMA-NEXT: lxvp vsp0, 0(r3)
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; CHECK-BE-NOMMA-NEXT: stxvp vsp0, 0(r4)
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; CHECK-BE-NOMMA-NEXT: blr
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entry:
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%0 = bitcast <256 x i1>* %vpp to i8*
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%1 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %0)
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%2 = bitcast <256 x i1>* %vp2 to i8*
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tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %1, i8* %2)
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ret void
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}
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declare <256 x i1> @llvm.ppc.vsx.lxvp(i8*)
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declare void @llvm.ppc.vsx.stxvp(<256 x i1>, i8*)
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define void @test_ldst_2(<256 x i1>* %vpp, i64 %offset, <256 x i1>* %vp2) {
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; CHECK-LABEL: test_ldst_2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxvpx vsp0, r3, r4
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; CHECK-NEXT: stxvpx vsp0, r5, r4
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; CHECK-NEXT: blr
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;
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; CHECK-NOMMA-LABEL: test_ldst_2:
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; CHECK-NOMMA: # %bb.0: # %entry
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; CHECK-NOMMA-NEXT: lxvpx vsp0, r3, r4
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; CHECK-NOMMA-NEXT: stxvpx vsp0, r5, r4
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; CHECK-NOMMA-NEXT: blr
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;
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; CHECK-BE-LABEL: test_ldst_2:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: lxvpx vsp0, r3, r4
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; CHECK-BE-NEXT: stxvpx vsp0, r5, r4
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; CHECK-BE-NEXT: blr
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;
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; CHECK-BE-NOMMA-LABEL: test_ldst_2:
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; CHECK-BE-NOMMA: # %bb.0: # %entry
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; CHECK-BE-NOMMA-NEXT: lxvpx vsp0, r3, r4
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; CHECK-BE-NOMMA-NEXT: stxvpx vsp0, r5, r4
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; CHECK-BE-NOMMA-NEXT: blr
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entry:
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%0 = bitcast <256 x i1>* %vpp to i8*
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%1 = getelementptr i8, i8* %0, i64 %offset
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%2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %1)
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%3 = bitcast <256 x i1>* %vp2 to i8*
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%4 = getelementptr i8, i8* %3, i64 %offset
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tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %2, i8* %4)
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ret void
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}
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define void @test_ldst_3(<256 x i1>* %vpp, <256 x i1>* %vp2) {
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; CHECK-LABEL: test_ldst_3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li r5, 18
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; CHECK-NEXT: lxvpx vsp0, r3, r5
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; CHECK-NEXT: stxvpx vsp0, r4, r5
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; CHECK-NEXT: blr
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;
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; CHECK-NOMMA-LABEL: test_ldst_3:
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; CHECK-NOMMA: # %bb.0: # %entry
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; CHECK-NOMMA-NEXT: li r5, 18
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; CHECK-NOMMA-NEXT: lxvpx vsp0, r3, r5
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; CHECK-NOMMA-NEXT: stxvpx vsp0, r4, r5
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; CHECK-NOMMA-NEXT: blr
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;
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; CHECK-BE-LABEL: test_ldst_3:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: li r5, 18
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; CHECK-BE-NEXT: lxvpx vsp0, r3, r5
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; CHECK-BE-NEXT: stxvpx vsp0, r4, r5
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; CHECK-BE-NEXT: blr
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;
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; CHECK-BE-NOMMA-LABEL: test_ldst_3:
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; CHECK-BE-NOMMA: # %bb.0: # %entry
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; CHECK-BE-NOMMA-NEXT: li r5, 18
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; CHECK-BE-NOMMA-NEXT: lxvpx vsp0, r3, r5
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; CHECK-BE-NOMMA-NEXT: stxvpx vsp0, r4, r5
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; CHECK-BE-NOMMA-NEXT: blr
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entry:
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%0 = bitcast <256 x i1>* %vpp to i8*
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%1 = getelementptr i8, i8* %0, i64 18
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%2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %1)
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%3 = bitcast <256 x i1>* %vp2 to i8*
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%4 = getelementptr i8, i8* %3, i64 18
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tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %2, i8* %4)
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ret void
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}
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define void @test_ldst_4(<256 x i1>* %vpp, <256 x i1>* %vp2) {
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; CHECK-LABEL: test_ldst_4:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li r5, 1
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; CHECK-NEXT: lxvpx vsp0, r3, r5
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; CHECK-NEXT: stxvpx vsp0, r4, r5
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; CHECK-NEXT: blr
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;
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; CHECK-NOMMA-LABEL: test_ldst_4:
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; CHECK-NOMMA: # %bb.0: # %entry
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; CHECK-NOMMA-NEXT: li r5, 1
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; CHECK-NOMMA-NEXT: lxvpx vsp0, r3, r5
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; CHECK-NOMMA-NEXT: stxvpx vsp0, r4, r5
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; CHECK-NOMMA-NEXT: blr
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;
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; CHECK-BE-LABEL: test_ldst_4:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: li r5, 1
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; CHECK-BE-NEXT: lxvpx vsp0, r3, r5
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; CHECK-BE-NEXT: stxvpx vsp0, r4, r5
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; CHECK-BE-NEXT: blr
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;
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; CHECK-BE-NOMMA-LABEL: test_ldst_4:
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; CHECK-BE-NOMMA: # %bb.0: # %entry
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; CHECK-BE-NOMMA-NEXT: li r5, 1
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; CHECK-BE-NOMMA-NEXT: lxvpx vsp0, r3, r5
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; CHECK-BE-NOMMA-NEXT: stxvpx vsp0, r4, r5
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; CHECK-BE-NOMMA-NEXT: blr
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entry:
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%0 = bitcast <256 x i1>* %vpp to i8*
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%1 = getelementptr i8, i8* %0, i64 1
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%2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %1)
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%3 = bitcast <256 x i1>* %vp2 to i8*
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%4 = getelementptr i8, i8* %3, i64 1
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tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %2, i8* %4)
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ret void
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}
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define void @test_ldst_5(<256 x i1>* %vpp, <256 x i1>* %vp2) {
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; CHECK-LABEL: test_ldst_5:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li r5, 42
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; CHECK-NEXT: lxvpx vsp0, r3, r5
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; CHECK-NEXT: stxvpx vsp0, r4, r5
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; CHECK-NEXT: blr
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;
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; CHECK-NOMMA-LABEL: test_ldst_5:
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; CHECK-NOMMA: # %bb.0: # %entry
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; CHECK-NOMMA-NEXT: li r5, 42
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; CHECK-NOMMA-NEXT: lxvpx vsp0, r3, r5
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; CHECK-NOMMA-NEXT: stxvpx vsp0, r4, r5
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; CHECK-NOMMA-NEXT: blr
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;
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; CHECK-BE-LABEL: test_ldst_5:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: li r5, 42
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; CHECK-BE-NEXT: lxvpx vsp0, r3, r5
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; CHECK-BE-NEXT: stxvpx vsp0, r4, r5
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; CHECK-BE-NEXT: blr
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;
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; CHECK-BE-NOMMA-LABEL: test_ldst_5:
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; CHECK-BE-NOMMA: # %bb.0: # %entry
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; CHECK-BE-NOMMA-NEXT: li r5, 42
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; CHECK-BE-NOMMA-NEXT: lxvpx vsp0, r3, r5
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; CHECK-BE-NOMMA-NEXT: stxvpx vsp0, r4, r5
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; CHECK-BE-NOMMA-NEXT: blr
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entry:
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%0 = bitcast <256 x i1>* %vpp to i8*
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%1 = getelementptr i8, i8* %0, i64 42
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%2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %1)
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%3 = bitcast <256 x i1>* %vp2 to i8*
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%4 = getelementptr i8, i8* %3, i64 42
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tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %2, i8* %4)
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ret void
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}
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||
|
|
|
||
|
|
define void @test_ldst_6(<256 x i1>* %vpp, <256 x i1>* %vp2) {
|
||
|
|
; CHECK-LABEL: test_ldst_6:
|
||
|
|
; CHECK: # %bb.0: # %entry
|
||
|
|
; CHECK-NEXT: lxvp vsp0, 4096(r3)
|
||
|
|
; CHECK-NEXT: stxvp vsp0, 4096(r4)
|
||
|
|
; CHECK-NEXT: blr
|
||
|
|
;
|
||
|
|
; CHECK-NOMMA-LABEL: test_ldst_6:
|
||
|
|
; CHECK-NOMMA: # %bb.0: # %entry
|
||
|
|
; CHECK-NOMMA-NEXT: lxvp vsp0, 4096(r3)
|
||
|
|
; CHECK-NOMMA-NEXT: stxvp vsp0, 4096(r4)
|
||
|
|
; CHECK-NOMMA-NEXT: blr
|
||
|
|
;
|
||
|
|
; CHECK-BE-LABEL: test_ldst_6:
|
||
|
|
; CHECK-BE: # %bb.0: # %entry
|
||
|
|
; CHECK-BE-NEXT: lxvp vsp0, 4096(r3)
|
||
|
|
; CHECK-BE-NEXT: stxvp vsp0, 4096(r4)
|
||
|
|
; CHECK-BE-NEXT: blr
|
||
|
|
;
|
||
|
|
; CHECK-BE-NOMMA-LABEL: test_ldst_6:
|
||
|
|
; CHECK-BE-NOMMA: # %bb.0: # %entry
|
||
|
|
; CHECK-BE-NOMMA-NEXT: lxvp vsp0, 4096(r3)
|
||
|
|
; CHECK-BE-NOMMA-NEXT: stxvp vsp0, 4096(r4)
|
||
|
|
; CHECK-BE-NOMMA-NEXT: blr
|
||
|
|
entry:
|
||
|
|
%0 = getelementptr <256 x i1>, <256 x i1>* %vpp, i64 128
|
||
|
|
%1 = bitcast <256 x i1>* %0 to i8*
|
||
|
|
%2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %1)
|
||
|
|
%3 = getelementptr <256 x i1>, <256 x i1>* %vp2, i64 128
|
||
|
|
%4 = bitcast <256 x i1>* %3 to i8*
|
||
|
|
tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %2, i8* %4)
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define void @test_ldst_7(<256 x i1>* %vpp, <256 x i1>* %vp2) {
|
||
|
|
; FIXME: A prefixed load (plxvp) is expected here as the offset in this
|
||
|
|
; test case is a constant that fits within 34-bits.
|
||
|
|
; CHECK-LABEL: test_ldst_7:
|
||
|
|
; CHECK: # %bb.0: # %entry
|
||
|
|
; CHECK-NEXT: li r5, 0
|
||
|
|
; CHECK-NEXT: ori r5, r5, 32799
|
||
|
|
; CHECK-NEXT: lxvpx vsp0, r3, r5
|
||
|
|
; CHECK-NEXT: stxvpx vsp0, r4, r5
|
||
|
|
; CHECK-NEXT: blr
|
||
|
|
;
|
||
|
|
; CHECK-NOMMA-LABEL: test_ldst_7:
|
||
|
|
; CHECK-NOMMA: # %bb.0: # %entry
|
||
|
|
; CHECK-NOMMA-NEXT: li r5, 0
|
||
|
|
; CHECK-NOMMA-NEXT: ori r5, r5, 32799
|
||
|
|
; CHECK-NOMMA-NEXT: lxvpx vsp0, r3, r5
|
||
|
|
; CHECK-NOMMA-NEXT: stxvpx vsp0, r4, r5
|
||
|
|
; CHECK-NOMMA-NEXT: blr
|
||
|
|
;
|
||
|
|
; CHECK-BE-LABEL: test_ldst_7:
|
||
|
|
; CHECK-BE: # %bb.0: # %entry
|
||
|
|
; CHECK-BE-NEXT: li r5, 0
|
||
|
|
; CHECK-BE-NEXT: ori r5, r5, 32799
|
||
|
|
; CHECK-BE-NEXT: lxvpx vsp0, r3, r5
|
||
|
|
; CHECK-BE-NEXT: stxvpx vsp0, r4, r5
|
||
|
|
; CHECK-BE-NEXT: blr
|
||
|
|
;
|
||
|
|
; CHECK-BE-NOMMA-LABEL: test_ldst_7:
|
||
|
|
; CHECK-BE-NOMMA: # %bb.0: # %entry
|
||
|
|
; CHECK-BE-NOMMA-NEXT: li r5, 0
|
||
|
|
; CHECK-BE-NOMMA-NEXT: ori r5, r5, 32799
|
||
|
|
; CHECK-BE-NOMMA-NEXT: lxvpx vsp0, r3, r5
|
||
|
|
; CHECK-BE-NOMMA-NEXT: stxvpx vsp0, r4, r5
|
||
|
|
; CHECK-BE-NOMMA-NEXT: blr
|
||
|
|
entry:
|
||
|
|
%0 = bitcast <256 x i1>* %vpp to i8*
|
||
|
|
%1 = getelementptr i8, i8* %0, i64 32799
|
||
|
|
%2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* %1)
|
||
|
|
%3 = bitcast <256 x i1>* %vp2 to i8*
|
||
|
|
%4 = getelementptr i8, i8* %3, i64 32799
|
||
|
|
tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %2, i8* %4)
|
||
|
|
ret void
|
||
|
|
}
|