81 lines
2.4 KiB
LLVM
81 lines
2.4 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; These test cases demonstrate that the vector shift quadword instructions
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; introduced within Power10 are correctly exploited.
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define dso_local <1 x i128> @test_vec_vslq(<1 x i128> %a, <1 x i128> %b) {
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; CHECK-LABEL: test_vec_vslq:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxswapd v3, v3
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; CHECK-NEXT: vslq v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%rem = urem <1 x i128> %b, <i128 128>
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%shl = shl <1 x i128> %a, %rem
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ret <1 x i128> %shl
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}
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define dso_local <1 x i128> @test_vec_vsrq(<1 x i128> %a, <1 x i128> %b) {
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; CHECK-LABEL: test_vec_vsrq:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxswapd v3, v3
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; CHECK-NEXT: vsrq v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%rem = urem <1 x i128> %b, <i128 128>
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%shr = lshr <1 x i128> %a, %rem
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ret <1 x i128> %shr
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}
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define dso_local <1 x i128> @test_vec_vsraq(<1 x i128> %a, <1 x i128> %b) {
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; CHECK-LABEL: test_vec_vsraq:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxswapd v3, v3
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; CHECK-NEXT: vsraq v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%rem = urem <1 x i128> %b, <i128 128>
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%shr = ashr <1 x i128> %a, %rem
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ret <1 x i128> %shr
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}
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define dso_local <1 x i128> @test_vec_vslq2(<1 x i128> %a, <1 x i128> %b) {
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; CHECK-LABEL: test_vec_vslq2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxswapd v3, v3
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; CHECK-NEXT: vslq v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%shl = shl <1 x i128> %a, %b
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ret <1 x i128> %shl
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}
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define dso_local <1 x i128> @test_vec_vsrq2(<1 x i128> %a, <1 x i128> %b) {
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; CHECK-LABEL: test_vec_vsrq2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxswapd v3, v3
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; CHECK-NEXT: vsrq v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%shr = lshr <1 x i128> %a, %b
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ret <1 x i128> %shr
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}
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define dso_local <1 x i128> @test_vec_vsraq2(<1 x i128> %a, <1 x i128> %b) {
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; CHECK-LABEL: test_vec_vsraq2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxswapd v3, v3
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; CHECK-NEXT: vsraq v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%shr = ashr <1 x i128> %a, %b
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ret <1 x i128> %shr
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}
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