274 lines
7.5 KiB
LLVM
274 lines
7.5 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; This test case aims to test the vector mask manipulation operations
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; on Power10.
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declare i32 @llvm.ppc.altivec.vextractbm(<16 x i8>)
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declare i32 @llvm.ppc.altivec.vextracthm(<8 x i16>)
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declare i32 @llvm.ppc.altivec.vextractwm(<4 x i32>)
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declare i32 @llvm.ppc.altivec.vextractdm(<2 x i64>)
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declare i32 @llvm.ppc.altivec.vextractqm(<1 x i128>)
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define i32 @test_vextractbm(<16 x i8> %a) {
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; CHECK-LABEL: test_vextractbm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vextractbm r3, v2
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; CHECK-NEXT: blr
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entry:
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%ext = tail call i32 @llvm.ppc.altivec.vextractbm(<16 x i8> %a)
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ret i32 %ext
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}
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define i32 @test_vextracthm(<8 x i16> %a) {
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; CHECK-LABEL: test_vextracthm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vextracthm r3, v2
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; CHECK-NEXT: blr
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entry:
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%ext = tail call i32 @llvm.ppc.altivec.vextracthm(<8 x i16> %a)
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ret i32 %ext
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}
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define i32 @test_vextractwm(<4 x i32> %a) {
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; CHECK-LABEL: test_vextractwm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vextractwm r3, v2
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; CHECK-NEXT: blr
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entry:
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%ext = tail call i32 @llvm.ppc.altivec.vextractwm(<4 x i32> %a)
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ret i32 %ext
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}
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define i32 @test_vextractdm(<2 x i64> %a) {
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; CHECK-LABEL: test_vextractdm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vextractdm r3, v2
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; CHECK-NEXT: blr
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entry:
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%ext = tail call i32 @llvm.ppc.altivec.vextractdm(<2 x i64> %a)
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ret i32 %ext
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}
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define i32 @test_vextractqm(<1 x i128> %a) {
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; CHECK-LABEL: test_vextractqm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vextractqm r3, v2
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; CHECK-NEXT: blr
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entry:
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%ext = tail call i32 @llvm.ppc.altivec.vextractqm(<1 x i128> %a)
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ret i32 %ext
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}
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declare <16 x i8> @llvm.ppc.altivec.vexpandbm(<16 x i8>)
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declare <8 x i16> @llvm.ppc.altivec.vexpandhm(<8 x i16>)
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declare <4 x i32> @llvm.ppc.altivec.vexpandwm(<4 x i32>)
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declare <2 x i64> @llvm.ppc.altivec.vexpanddm(<2 x i64>)
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declare <1 x i128> @llvm.ppc.altivec.vexpandqm(<1 x i128>)
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define <16 x i8> @test_vexpandbm(<16 x i8> %a) {
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; CHECK-LABEL: test_vexpandbm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vexpandbm v2, v2
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; CHECK-NEXT: blr
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entry:
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%exp = tail call <16 x i8> @llvm.ppc.altivec.vexpandbm(<16 x i8> %a)
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ret <16 x i8> %exp
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}
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define <8 x i16> @test_vexpandhm(<8 x i16> %a) {
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; CHECK-LABEL: test_vexpandhm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vexpandhm v2, v2
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; CHECK-NEXT: blr
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entry:
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%exp = tail call <8 x i16> @llvm.ppc.altivec.vexpandhm(<8 x i16> %a)
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ret <8 x i16> %exp
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}
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define <4 x i32> @test_vexpandwm(<4 x i32> %a) {
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; CHECK-LABEL: test_vexpandwm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vexpandwm v2, v2
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; CHECK-NEXT: blr
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entry:
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%exp = tail call <4 x i32> @llvm.ppc.altivec.vexpandwm(<4 x i32> %a)
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ret <4 x i32> %exp
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}
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define <2 x i64> @test_vexpanddm(<2 x i64> %a) {
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; CHECK-LABEL: test_vexpanddm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vexpanddm v2, v2
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; CHECK-NEXT: blr
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entry:
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%exp = tail call <2 x i64> @llvm.ppc.altivec.vexpanddm(<2 x i64> %a)
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ret <2 x i64> %exp
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}
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define <1 x i128> @test_vexpandqm(<1 x i128> %a) {
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; CHECK-LABEL: test_vexpandqm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vexpandqm v2, v2
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; CHECK-NEXT: blr
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entry:
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%exp = tail call <1 x i128> @llvm.ppc.altivec.vexpandqm(<1 x i128> %a)
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ret <1 x i128> %exp
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}
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declare i64 @llvm.ppc.altivec.vcntmbb(<16 x i8>, i32)
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declare i64 @llvm.ppc.altivec.vcntmbh(<8 x i16>, i32)
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declare i64 @llvm.ppc.altivec.vcntmbw(<4 x i32>, i32)
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declare i64 @llvm.ppc.altivec.vcntmbd(<2 x i64>, i32)
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define i64 @test_vcntmbb(<16 x i8> %a) {
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; CHECK-LABEL: test_vcntmbb:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vcntmbb r3, v2, 1
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; CHECK-NEXT: blr
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entry:
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%cnt = tail call i64 @llvm.ppc.altivec.vcntmbb(<16 x i8> %a, i32 1)
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ret i64 %cnt
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}
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define i64 @test_vcntmbh(<8 x i16> %a) {
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; CHECK-LABEL: test_vcntmbh:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vcntmbh r3, v2, 0
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; CHECK-NEXT: blr
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entry:
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%cnt = tail call i64 @llvm.ppc.altivec.vcntmbh(<8 x i16> %a, i32 0)
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ret i64 %cnt
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}
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define i64 @test_vcntmbw(<4 x i32> %a) {
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; CHECK-LABEL: test_vcntmbw:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vcntmbw r3, v2, 1
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; CHECK-NEXT: blr
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entry:
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%cnt = tail call i64 @llvm.ppc.altivec.vcntmbw(<4 x i32> %a, i32 1)
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ret i64 %cnt
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}
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define i64 @test_vcntmbd(<2 x i64> %a) {
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; CHECK-LABEL: test_vcntmbd:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vcntmbd r3, v2, 0
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; CHECK-NEXT: blr
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entry:
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%cnt = tail call i64 @llvm.ppc.altivec.vcntmbd(<2 x i64> %a, i32 0)
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ret i64 %cnt
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}
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declare <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64)
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declare <8 x i16> @llvm.ppc.altivec.mtvsrhm(i64)
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declare <4 x i32> @llvm.ppc.altivec.mtvsrwm(i64)
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declare <2 x i64> @llvm.ppc.altivec.mtvsrdm(i64)
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declare <1 x i128> @llvm.ppc.altivec.mtvsrqm(i64)
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define <16 x i8> @test_mtvsrbm(i64 %a) {
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; CHECK-LABEL: test_mtvsrbm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrbm v2, r3
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; CHECK-NEXT: blr
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entry:
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%mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 %a)
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ret <16 x i8> %mv
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}
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define <16 x i8> @test_mtvsrbmi() {
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; CHECK-LABEL: test_mtvsrbmi:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrbmi v2, 1
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; CHECK-NEXT: blr
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entry:
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%mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 1)
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ret <16 x i8> %mv
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}
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define <16 x i8> @test_mtvsrbmi2() {
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; CHECK-LABEL: test_mtvsrbmi2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrbmi v2, 255
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; CHECK-NEXT: blr
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entry:
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%mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 255)
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ret <16 x i8> %mv
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}
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define <16 x i8> @test_mtvsrbmi3() {
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; CHECK-LABEL: test_mtvsrbmi3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrbmi v2, 65535
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; CHECK-NEXT: blr
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entry:
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%mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 65535)
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ret <16 x i8> %mv
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}
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define <16 x i8> @test_mtvsrbmi4() {
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; CHECK-LABEL: test_mtvsrbmi4:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrbmi v2, 0
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; CHECK-NEXT: blr
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entry:
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%mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 65536)
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ret <16 x i8> %mv
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}
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define <16 x i8> @test_mtvsrbmi5() {
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; CHECK-LABEL: test_mtvsrbmi5:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrbmi v2, 10
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; CHECK-NEXT: blr
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entry:
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%mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 65546)
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ret <16 x i8> %mv
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}
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define <8 x i16> @test_mtvsrhm(i64 %a) {
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; CHECK-LABEL: test_mtvsrhm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrhm v2, r3
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; CHECK-NEXT: blr
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entry:
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%mv = tail call <8 x i16> @llvm.ppc.altivec.mtvsrhm(i64 %a)
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ret <8 x i16> %mv
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}
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define <4 x i32> @test_mtvsrwm(i64 %a) {
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; CHECK-LABEL: test_mtvsrwm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrwm v2, r3
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; CHECK-NEXT: blr
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entry:
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%mv = tail call <4 x i32> @llvm.ppc.altivec.mtvsrwm(i64 %a)
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ret <4 x i32> %mv
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}
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define <2 x i64> @test_mtvsrdm(i64 %a) {
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; CHECK-LABEL: test_mtvsrdm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrdm v2, r3
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; CHECK-NEXT: blr
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entry:
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%mv = tail call <2 x i64> @llvm.ppc.altivec.mtvsrdm(i64 %a)
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ret <2 x i64> %mv
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}
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define <1 x i128> @test_mtvsrqm(i64 %a) {
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; CHECK-LABEL: test_mtvsrqm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrqm v2, r3
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; CHECK-NEXT: blr
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entry:
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%mv = tail call <1 x i128> @llvm.ppc.altivec.mtvsrqm(i64 %a)
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ret <1 x i128> %mv
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}
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