llvm-for-llvmta/test/CodeGen/PowerPC/mi-peephole.mir

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2022-04-25 10:02:23 +02:00
# RUN: llc -mtriple=powerpc64le--linux-gnu -run-pass ppc-mi-peepholes %s -o - \
# RUN: -verify-machineinstrs | FileCheck %s
---
name: testRLDIC
alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc }
- { id: 1, class: g8rc }
- { id: 2, class: g8rc }
liveins:
- { reg: '$x3', virtual-reg: '%0' }
- { reg: '$x4', virtual-reg: '%1' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
body: |
body: |
bb.0.entry:
liveins: $x3, $x4
%1:g8rc = COPY $x4
%0:g8rc = COPY $x3
%2:g8rc = RLDICL killed %1, 0, 32
%3:g8rc = RLDICR %2, 2, 61
$x3 = COPY %3
BLR8 implicit $lr8, implicit $rm, implicit $x3
; CHECK-LABEL: testRLDIC
; CHECK: bb.0.entry:
; CHECK: %1:g8rc = COPY $x4
; CHECK: %0:g8rc = COPY $x3
; CHECK: %3:g8rc = RLDIC killed %1, 2, 30
; CHECK: $x3 = COPY %3
; CHECK: BLR8 implicit $lr8, implicit $rm, implicit $x3
...